SNVSCE2B May   2023  – November 2023 LP5868T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
        1. 7.3.2.1 Global 3-Bits Maximum Current (MC) Setting
        2. 7.3.2.2 3 Groups of 7-Bits Color Current (CC) Setting
        3. 7.3.2.3 Individual 8-bit Dot Current (DC) Setting
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 Individual 8-Bit / 16-Bit PWM for Each LED Dot
        2. 7.3.3.2 Programmable Groups of 8-Bit PWM Dimming
        3. 7.3.3.3 8-Bit PWM for Global Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
        1. 7.3.7.1 LED Open Detection
        2. 7.3.7.2 LED Short Detection
        3. 7.3.7.3 Thermal Shutdown
        4. 7.3.7.4 UVLO (Under Voltage Lock Out)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Interface Selection
      2. 7.5.2 I2C Interface
        1. 7.5.2.1 I2C Data Transactions
        2. 7.5.2.2 I2C Data Format
        3. 7.5.2.3 Multiple Devices Connection
      3. 7.5.3 Programming
        1. 7.5.3.1 SPI Data Transactions
        2. 7.5.3.2 SPI Data Format
        3. 7.5.3.3 Multiple Devices Connection
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 VDD Input Supply Recommendations
      2. 8.3.2 VLED Input Supply Recommendations
      3. 8.3.3 VIO Input Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

MIN NOM MAX UNIT
MISC. Timming Requirements
fOSC Internal oscillator frequency 31.2 MHz
fOSC _ERR Device to device oscillator frequency error –3% 3%
tPOR_H Wait time from UVLO disactive to device NORMAL 500 µs
tCHIP_EN Wait time from setting Chip_EN (Register) =1 to device NORMAL 100 µs
tRISE LED output rise time 10 ns
tFALL LED output fall time 15 ns
tVSYNC_H The minimum high-level pulse width of VSYNC 200 µs
SPI timing requirements
fSCLK SPI Clock frequency 12 MHz
1 Cycle time 83.3 ns
2 SS active lead-time 50 ns
3 SS active leg time 50 ns
4 SS inactive time 50 ns
5 SCLK low time 36 ns
6 SCLK high time 36 ns
7 MOSI set-up time 20 ns
8 MOSI hold time 20 ns
9 MISO disable time 30 ns
10 MISO data valid time 35 ns
Cb Bus capacitance 5 40 pF
I2C fast mode timing requirements
fSCL I2C clock frequency 0 400 KHz
1 Hold time (repeated) START condition 600 ns
2 Clock low time 1300 ns
3 Clock high time 600 ns
4 Setup time for a repeated START condition 600 ns
5 Data hold time 0 ns
6 Data setup time 100 ns
7 Rise time of SDA and SCL 300 ns
8 Fall time of SDA and SCL 300 ns
9 Setup time for STOP condition 600 ns
10 Bus free time between a STOP and a START condition 1.3 µs
I2C fast mode plus timing requirements
fSCL I2C clock frequency 0 1000 KHz
1 Hold time (repeated) START condition 260 ns
2 Clock low time 500 ns
3 Clock high time 260 ns
4 Setup time for a repeated START condition 260 ns
5 Data hold time 0 ns
6 Data setup time 50 ns
7 Rise time of SDA and SCL 120 ns
8 Fall time of SDA and SCL 120 ns
9 Setup time for STOP condition 260 ns
10 Bus free time between a STOP and a START condition 0.5 µs