SNVSC61A August   2022  – December 2022 LP5891-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Independent and Stackable Mode
        1. 8.3.1.1 Independent Mode
        2. 8.3.1.2 Stackable Mode
      2. 8.3.2 Current Setting
        1. 8.3.2.1 Brightness Control (BC) Function
        2. 8.3.2.2 Color Brightness Control (CC) Function
        3. 8.3.2.3 Choosing BC/CC for a Different Application
      3. 8.3.3 Frequency Multiplier
      4. 8.3.4 Line Transitioning Sequence
      5. 8.3.5 Protections and Diagnostics
        1. 8.3.5.1 Thermal Shutdown Protection
        2. 8.3.5.2 IREF Resistor Short Protection
        3. 8.3.5.3 LED Open Load Detection and Removal
          1. 8.3.5.3.1 LED Open Detection
          2. 8.3.5.3.2 Read LED Open Information
          3. 8.3.5.3.3 LED Open Caterpillar Removal
        4. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 8.3.5.4.1 LED Short/Weak Short Detection
          2. 8.3.5.4.2 Read LED Short Information
          3. 8.3.5.4.3 LSD Caterpillar Removal
    4. 8.4 Device Functional Modes
    5. 8.5 Continuous Clock Series Interface
      1. 8.5.1 Data Validity
      2. 8.5.2 CCSI Frame Format
      3. 8.5.3 Write Command
        1. 8.5.3.1 Chip Index Write Command
        2. 8.5.3.2 VSYNC Write Command
        3. 8.5.3.3 MPSM Write Command
        4. 8.5.3.4 Standby Clear and Enable Command
        5. 8.5.3.5 Soft_Reset Command
        6. 8.5.3.6 Data Write Command
      4. 8.5.4 Read Command
    6. 8.6 PWM Grayscale Control
      1. 8.6.1 Grayscale Data Storage and Display
        1. 8.6.1.1 Memory Structure Overview
        2. 8.6.1.2 Details of Memory Bank
        3. 8.6.1.3 Write a Frame Data into Memory Bank
      2. 8.6.2 PWM Control for Display
    7. 8.7 Register Maps
      1. 8.7.1  FC0
      2. 8.7.2  FC1
      3. 8.7.3  FC2
      4. 8.7.4  FC3
      5. 8.7.5  FC4
      6. 8.7.6  FC14
      7. 8.7.7  FC15
      8. 8.7.8  FC16
      9. 8.7.9  FC17
      10. 8.7.10 FC18
      11. 8.7.11 FC19
      12. 8.7.12 FC20
      13. 8.7.13 FC21
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 System Structure
        2. 9.2.1.2 SCLK Frequency
        3. 9.2.1.3 Internal GCLK Frequency
        4. 9.2.1.4 Line Switch Time
        5. 9.2.1.5 Blank Time Removal
        6. 9.2.1.6 BC and CC
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Chip Index Command
        2. 9.2.2.2 FC Registers Settings
        3. 9.2.2.3 Grayscale Data Write
        4. 9.2.2.4 VSYNC Command
        5. 9.2.2.5 LED Open, Short Read
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1.2 Stackable Mode

While operating the LP5891-Q1 in stackable mode, as shown in below table.

Table 8-1 Stackable Mode
ModeMatrix SizeRegister ValueScan Sequence
Mode116x32000bD1, D2 independent
Mode232x32001bD1->D2
Mode348x48010bD1->D2->D3
Mode448x48011bD1->D3->D2
Mode548x64100bD1->D2->D3
Mode648x64101bD1->D3->D2
Mode764x64110bD1->D2->D3->D4
Mode864x64111bD1->D4->D2->D3

Figure 8-2 device 2 needs to be rotated 180o relative to device 1. This action allows the position of line switches to be near the center column of the LED matrix for better routing. For device 1, the lines connect sequentially (line switch 0 connected to scan line 1). However on device 2, it is connected in reverse order, with the 16th scan line is connected to line switch 15 and the 32nd scan line is connected to line switch 0.

Figure 8-2 shows the connection between two LP5891-Q1 devices in stackable mode driving 32 × 32 RGB LED pixels. The MOD_SIZE must be configured to 001b. Device 1 supplies 16 line switches for the first 16 scan line, and device 2 supplies 16 line switches for scan line 17-32. The data for matrix sections A and C are stored in device 1, while matrix sections B and D data are stored in device 2.

To make sure the scanning sequence is still from 1st line to 32nd line, the scan line switching order of the second device must be reversed, which can be configured by the SCAN_REV (see FC4 for more details).

GUID-075972BF-8DE8-4EBB-A67C-2494142E20FF-low.gifFigure 8-2 Mode2 Diagram
GUID-86D77C8F-72FA-41C6-BEC8-D7BF70DD56CB-low.gifFigure 8-3 Mode3 and Mode4 Diagram
GUID-CCE3B249-716B-4343-AD67-3F6D7F9ECC03-low.gifFigure 8-4 Mode5 and Mode6 Diagram
GUID-E3AFFF10-75E5-4E50-A2A6-2AB431AD9373-low.gifFigure 8-5 Mode7 and Mode8 Diagram

When two or more LP5891-Q1 devices are used in stackable mode, if there are unused line switches, these unused line switches must be the last line switches of the first or the second device. For example, if there are only 30 scanning lines, and if,

SCAN_REV = '0'b, the unused line switches can be either of the below,

  • 1_LS14, 1_LS15
  • 2_LS14, 2_LS15

SCAN_REV = '1'b, the unused line switches can be either of below,

  • 1_LS14, 1_LS15
  • 2_LS1, 2_LS0

The unused line switches must be 2_LS14, 2_LS15 if SCAN_REV = '0'b, or 2_LS1, 2_LS0 if SCAN_REV = '1'b.