SNVSA91F September   2015  – April 2021 LP5910

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 No-Load Stability
      2. 7.3.2 Thermal Overload Protection
      3. 7.3.3 Short-Circuit Protection
      4. 7.3.4 Output Automatic Discharge
      5. 7.3.5 Reverse Current Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable (EN)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Capacitor Characteristics
        5. 8.2.2.5 Remote Capacitor Operation
        6. 8.2.2.6 No-Load Stability
        7. 8.2.2.7 Enable Control
        8. 8.2.2.8 Power Dissipation
        9. 8.2.2.9 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 DSBGA Mounting
      2. 10.1.2 DSBGA Light Sensitivity
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VIN = VOUT(NOM) + 0.5 V, VEN = 1 V, IOUT = 1 mA, CIN = 1 µF, and COUT = 1 µF (unless otherwise noted)(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
ΔVOUT Output voltage tolerance VIN = (VOUT(NOM) + 0.5 V) to 3.3 V,
IOUT = 1 mA to 300 mA		 –2 2 %VOUT
Line regulation VIN = (VOUT(NOM) + 0.5 V) to 3.3 V,
IOUT = 1 mA		 0.01 %/V
Load regulation IOUT = 1 mA to 300 mA 0.002 %/mA
ILOAD Load current See(4) 0 300 mA
IQ Quiescent current(5) VEN = 1 V, IOUT = 0 mA 12 25 µA
VEN = 1 V, IOUT = 300 mA 230 350
IQ(SD) Quiescent current in shutdown(5) VEN = 0.3 V, –40°C ≤ TJ ≤ 85°C 0.02 2
IRO Output reverse current(7)
VOUT > VIN		 VOUT = 3.3 V, VIN = VEN = 0 V –20 0 µA
VOUT = 3.3 V, VIN = VEN = 1.3 V 0 50 µA
IG Ground current(6) IOUT = 0 mA (VOUT = 2.3 V) 15 µA
VDO Dropout voltage(8) 1.3 V ≤ VOUT < 1.5 V,
IOUT = 300 mA		 DSBGA only 200 300 mV
1.5 V ≤ VOUT <1.8V,
IOUT = 300 mA

DSBGA only

160

235
1.8 V ≤ VOUT ≤ 2.3 V,
IOUT = 300 mA		 DSBGA only 120 180
1.3 V ≤ VOUT < 1.5 V,
IOUT = 300 mA		 WSON only 245 370
1.5 V ≤ VOUT < 1.8V,
IOUT = 300 mA

WSON only

195

270
1.8 V ≤ VOUT ≤ 2.3 V,
IOUT = 300 mA		 WSON only 145 220
ILIMIT Output current limit VOUT = VOUT(NOM) – 0.1 V
VIN = VOUT(NOM) + 0.5 V		 450 mA
PSRR Power supply rejection ratio(10) ƒ = 100 Hz, IOUT = 20 mA, VOUT ≥ 1 V 80 dB
ƒ = 1 kHz, IOUT = 20 mA, VOUT ≥ 1 V 75
ƒ = 10 kHz, IOUT = 20 mA, VOUT ≥ 1 V 65
ƒ = 100 kHz, IOUT = 20 mA, VOUT ≥ 1 V 40
ƒ = 2 MHz, IOUT = 20 mA, VOUT ≥ 1 V 25
ƒ = 100 Hz, IOUT = 20 mA, 0.8 V < VOUT < 1 V 65
ƒ = 1 kHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V 65
ƒ = 10 kHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V 65
ƒ = 100 kHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V 40
ƒ = 2 MHz, IOUT = 20 mA, 0.8 V < VOUT < 1 V 25
eN Output noise voltage(10) BW = 10 Hz to 100 kHz IOUT = 1 mA 12 µVRMS
IOUT = 300 mA 12
TSD Thermal shutdown TJ rising until output is OFF 160 °C
Thermal hysteresis TJ falling from shutdown 15
LOGIC INPUT THRESHOLDS
VIL EN low threshold (Off) VIN = 1.3 V to 3.3 V 0.3 V
VIH EN high threshold (On) 1
IEN EN pin current(9) VEN = 3.3 V, VIN = 3.3 V 3.3 µA
VEN = 0 V, VIN = 3.3 V 0.001
TRANSIENT CHARACTERISTICS(9)
ΔVOUT Line transient(10) VIN = (VOUT(NOM) + 0.5 V) to (VOUT(NOM) + 1 V) in 30 µs
IOUT = 1 mA		 0 1 mV
VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) + 0.5 V) in 30 µs
IOUT = 1 mA		 –1 0
Load transient(10) IOUT = 1 mA to 100 mA in 10 µs –45 mV
IOUT = 100 mA to 1 mA in 10 µs 45
Overshoot on start-up(10) 5%
tON Turnon time From VEN > VIH to VOUT = 95% of VOUT(NOM) 80 200 µs
OUTPUT DISCHARGE
RAD Output discharge pulldown resistance VEN = 0 V, VIN = 2.3 V 160 Ω
(1) All voltages are with respect to the device GND pin.
(2) Minimum and maximum limits are ensured through test, design, or statistical correlation over the TJ range of –40°C to 125°C, unless otherwise stated. Typical values represent the most likely parametric norm at TA = 25°C, and are provided for reference purposes only.
(3) CIN, COUT: Low-ESR Surface-Mount-Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(4) The device maintains a stable, regulated output voltage without a load current.
(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT. IQ = (IIN – IOUT)
(6) Ground current is defined here as the total current flowing to ground as a result of all input voltages applied to the device.
(7) Output reverse current (IRO) is measured at the IN pin.
(8) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value. Dropout voltage is not a valid condition for output voltages less than 1.3 V as compliance with the minimum operating input voltage can not be ensured.
(9) There is a 1-MΩ resistor between EN and ground on the device.
(10) This specification is verified by design.