The LP5922 is 2-A low dropout (LDO) linear regulator with 200-mV typical dropout voltage at maximum current levels. The LP5922 device can operate from a voltage rail down to 1.3 V without additional bias supply. System efficiency is maximized and power dissipation minimized by the low dropout and low VIN capability. The device also features low quiescent current and very low shutdown current.
The LP5922 device was designed to have high PSRR and low output noise to support sensitive analog applications without additional filtering. The output noise can be reduced even further by implementing a small capacitor on the SS/NR pin.
The output voltage is adjustable from 0.5 V to 5 V by an external resistor divider. Enable pin, adjustable soft start and optional Power Good features help with system power sequencing. Inrush current is controlled with the soft start and the device has short circuit and thermal protections.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP5922 | WSON (10) | 3.00 mm × 3.00 mm |
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Changes from * Revision (November 2016) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NUMBER | NAME | ||
1 | OUT | O | Regulated output voltage, connect directly to pin 2 |
2 | OUT | O | Regulated output voltage, connect directly to pin 1 |
3 | FB | I | Voltage feedback input to the internal error amplifier |
4 | GND | Ground | Ground; connect to device pin 8. |
5 | PG | O | Power Good to indicate the status of output voltage. Requires an external pullup resistor. When PG pin voltage is high the output voltage is considered good. |
6 | EN | I | Enable |
7 | SS/NR | I/O | Soft-start and noise reduction pin |
8 | GND | Ground | Ground —connect to device pin 4. |
9 | IN | I | Supply voltage input — connect directly to pin 10. |
10 | IN | I | Supply voltage input —connect directly to pin 9. |
Exposed pad | Thermal Pad | — | The exposed thermal pad on the bottom of the package must be connected to a copper area under the package on the PCB. Connect to ground potential. Do not connect to any potential other than the same ground potential seen at device pins 4 and 8 (GND). See Power Dissipation for more information. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
IN pin voltage, VIN | –0.3 | 7 | V | |
OUT pin voltage, VOUT | See(3) | |||
EN pin voltage, VEN | –0.3 | 7 | V | |
PG pin voltage, VPG | –0.3 | 7 | V | |
SS/NR pin voltage, VSS/NR | –0.3 | 3.6 | V | |
FB pin voltage, VFB | –0.3 | 3.6 | V | |
Junction temperature, TJ | 150 | °C | ||
Continuous power dissipation(4) | Internally limited | |||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Input voltage, VIN | 1.3 | 6 | V | ||
Output voltage, VOUT | 0.5 | 5 | V | ||
FB voltage, VFB | 0.5 | V | |||
EN input voltage, VEN | 0 | VIN | V | ||
Recommended load current, IL | 0 | 2 | A | ||
Operating junction temperature, TJ-MAX-OP | –40 | 125 | °C |
THERMAL METRIC(1) | LP5922 | UNIT | |
---|---|---|---|
DSC (WSON) | |||
10 PINS | |||
RθJA(2) | Junction-to-ambient thermal resistance, High K | 49.5(3) | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 38.2 | °C/W |
RθJB | Junction-to-board thermal resistance | 24.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 24.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.0 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE | ||||||
VIN | Input voltage range | 1.3 | 6 | V | ||
UVLO | Undervoltage lock-out threshold | VIN Rising (↑) until output is ON | 1.2 | 1.25 | V | |
ΔUVLO | UVLO hysteresis | VIN Falling (↓) from UVLO threshold until output is OFF | 160 | mV | ||
OUTPUT VOLTAGE AND REGULATION | ||||||
VOUT | Output voltage range | 0.5 | 5 | V | ||
ΔVOUT | Line regulation | IOUT = 5 mA, 1.3 V ≤ VIN ≤ 6 V | 0.02 | %/V | ||
Load regulation | 5 mA ≤ IOUT ≤ 2 A | 0.1 | %/A | |||
VDO | Dropout voltage(4) | VIN = 1.4 V, IOUT = 2 A | 220 | 400 | mV | |
VIN = 2.5 V, IOUT = 2 A | 100 | 180 | ||||
VIN = 5.3 V, IOUT = 2 A | 90 | 160 | ||||
FB | ||||||
VFB | FB voltage | IOUT = 5 mA to 2 A | 492.5 | 500 | 507.5 | mV |
IFB | FB pin input current | VFB = 0.5 V | –100 | 100 | nA | |
CURRENT LEVELS | ||||||
IL | Maximum load current | VIN ≥ 1.3 V | 2 | A | ||
ISC | Short-circuit current limit(5) | 2.2 | 3 | 3.8 | A | |
IGND | Ground-current minimum load(7) | VIN = 6 V, IOUT = 0 mA | 0.7 | mA | ||
Ground-current maximum load(7) | VIN = 1.3 V, IOUT = 2 A | 1 | 4 | |||
IGND(SD) | Shutdown current(6) | VIN = 6 V, VEN = 0 V, VPG = 0 V | 0.1 | 15 | µA | |
VIN to VOUT RIPPLE REJECTION (9) | ||||||
PSRR | Power-supply rejection ratio | VIN ≥ 1.4 V, ƒ = 1 kHz, IOUT = 2 A | 70 | dB | ||
VIN ≥ 1.4 V, ƒ = 10 kHz, IOUT = 2 A | 55 | |||||
VIN ≥ 1.4 V, ƒ = 100 kHz, IOUT = 2 A | 40 | |||||
VIN ≥ 1.4 V, ƒ = 1 MHz, IOUT = 2 A | 30 | |||||
OUTPUT NOISE VOLTAGE | ||||||
eN | Noise voltage(9) | VIN= 2.5 V, VOUT= 1.8 V BW = 10 Hz to 100 kHz |
25 | µVRMS | ||
LOGIC INPUT THRESHOLDS | ||||||
VIL(EN) | EN pin low threshold | VEN falling (↓) until output is OFF | 0.35 | V | ||
VIH(EN) | EN pin high threshold | VEN rising (↑) until output is ON | 1.2 | V | ||
IEN | Input current at EN pin (8) | VIN = 6 V, VEN = 6 V | 3 | µA | ||
PGHTH | PG high threshold (% of nominal VOUT) | VOUT rising (↑) until PG goes high | 94% | |||
PGLTH | PG low threshold (% of nominal VOUT) | VOUT falling (↓) until PG goes low | 90% | |||
VOL(PG) | PG pin low-level output voltage | VOUT < PGLTH, sink current = 1 mA | 400 | mV | ||
ILKG(PG) | PG pin leakage current | VOUT > PGHTH, VPG = 6 V | 1 | µA | ||
SOFT START | ||||||
ISS | SS/NR pin charging current | 6.2 | µA | |||
THERMAL SHUTDOWN | ||||||
TSD | Thermal shutdown temperature | 165 | °C | |||
ΔTSD | Thermal shutdown hysteresis | 15 | °C | |||
TRANSITION CHARACTERISTICS | ||||||
ΔVOUT | Line transients | ΔVIN = 0.5 V, VOUT = 2.8 V, tRISE = tFALL = 5 μs |
3 | mV | ||
Load transients | VOUT = 2.8 V, IOUT = 10 mA to 2 A to 10 mA tRISE = tFALL = 1 A/μs |
25 | ||||
RAD | Output discharge pull-down resistance | VEN = 0 V, VIN = 2.3 V | 400 | Ω |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
CIN | Input capacitance(1) | 22 | µF | |||
COUT | Output capacitance | VOUT ≤ 0.8 V | 34 | 47 | µF | |
VOUT > 0.8 V | 15 | 22 |
VOUT = 5 V | VEN = VIN | IOUT = 1 mA |
VOUT = 5 V | VEN = VIN | IOUT = 1 mA |
VOUT = 5 V | IOUT = 1 mA |
VIN = 5.5 V | VOUT = 5 V |
VOUT = 5 V | VEN = VIN | IOUT = 2 A |
VOUT = 5 V | VEN = VIN | IOUT = 2 A |
VOUT = 5 V | IOUT = 2 A |
VIN = 2.5 V | VOUT = 1.8 V |
The LP5922 is a low-noise, high PSRR, low-dropout regulator capable of sourcing a 2-A load. The LP5922 can operate down to 1.3-V input voltage and 0.5-V output voltage. This combination of low noise, high PSRR, and low output voltage makes the device an ideal low dropout (LDO) regulator to power a multitude of loads from noise-sensitive communication components to battery-powered system.
The LP5922 block diagram contains several features, including:
The LP5922 output voltage can be set to any value from 0.5 V to 5 V using two external resistors shown as RUPPER and RLOWER in Figure 15. The value for the RLOWER should be less than or equal to 100 kΩ for good loop compensation. RUPPER can be selected for a given VOUT using Equation 1:
where
The LP5922 EN pin is internally held low by a 2-MΩ resistor to GND. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. The EN pin voltage must be lower than the VIL threshold to ensure that the device is fully disabled and the automatic output discharge is activated.
The LP5922 output employs an internal 400-Ω (typical) pulldown resistance to discharge the output capacitor when the EN pin is low, and the device is disabled.
The output voltage of LP5922 ramps up linearly in a constant slew rate until reaching the target regulating voltage after a stable VIN (greater than VOUT + VDO) is supplied and EN pin is pulled high. The slew rate of VOUT ramping is programmable by an external capacitor on the SS/NR pin; therefore, the duration for soft-start period is programmable as well. Once the LP5922 is enabled, the SS/NR pin sources a constant 6-µA current to charge the external CSS/NR capacitor until the voltage at the SS/NR pin reaches 98% of the internal reference voltage (VREF) of 500 mV typical. The final 2% of CSS/NR charge is determined by a RC time constant. During the soft-start period, the current flowing into the IN pin primarily consists of the sum of the load current at the LDO output and the charging current into the output capacitor. The soft-start period can be calculated by Equation 2:
where
The recommended value for CSS/NR is 100 nF or larger. Equation 2 is most accurate for these values. The CSS/NR capacitor is also the filter capacitor for internal reference for noise reduction purpose. An integrated resistor and the CSS/NR capacitor structure a RC low-pass filter to remove the noise on the internal reference voltage.
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The LDO is not designed to operate in a steady-state current limit. During a current-limit event, the LDO sources constant current. Therefore, the output voltage falls when load impedance decreases. Note also that if a current limit occurs and the resulting output voltage is low, excessive power may be dissipated across the LDO, resulting in a thermal shutdown of the output.
Thermal shutdown disables the output when the junction temperature rises to TSD level, which allows the device to cool. When the junction temperature cools by ΔTSD, the output circuitry enables. Based on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This thermal cycling limits the dissipation of the regulator and protects it from damage as a result of overheating.
The internal protection circuitry of the LP5922 is designed to protect against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the LP5922 into thermal shutdown degrades device reliability.
The LP5922 has a Power-Good function that works by toggling the state of the PG output pin. When the output voltage falls below the PG threshold voltage (PGLTH), the PG pin open-drain output engages (low impedance to GND). When the output voltage rises above the PG threshold voltage (PGHTH), the PG pin becomes high-impedance. By connecting a pullup resistor to an external supply, any downstream device can receive PG as a logic signal. User must make sure that the external pullup supply voltage results in a valid logic signal for the receiving device or devices; use a pullup resistor from 10 kΩ to 100 kΩ for best results.
In Power-Good function, the PG output pin pulled high immediatelly after output voltage rises above the PG threshold voltage.
The LP5922 enable (EN) pin is internally held low by a 2-MΩ resistor to GND. If the EN pin is open the output is OFF. The EN pin voltage must be higher than the VIH threshold to ensure that the device is fully enabled under all operating conditions. When the EN pin is pulled low, and the output is disabled, the output automatic discharge circuit is activated. Any charge on the OUT pin is discharged to GND through the internal pulldown resistance.
The LP5922 incorporates UVLO. The UVLO circuit monitors the input voltage and keeps the LP5922 disabled while a rising VIN is less than 1.2 V (typical). The rising UVLO threshold is approximately 100 mV below the recommended minimum operating VIN of 1.3 V.
The LP5922 internal circuit is not fully functional until VIN is at least 1.3 V. The output voltage is not regulated until VIN has reached at least the greater of 1.3 V or (VOUT + VDO).
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LP5922 is designed to meet the requirements of RF and analog circuits, by providing low noise, high PSRR, low quiescent current, and low line or load transient response figures. The device offers excellent noise performance without the need for a noise bypass capacitor and is stable with input and output capacitors with a value of 22 µF. The LP5922 delivers this performance in an industry-standard WSON package which, for this device, is specified with an operating junction temperature (TJ) of –40°C to +125°C.
Figure 15 shows the typical application circuit for the LP5922. Input and output capacitances may need to be increased above 22 µF minimum for some applications.
For typical LP5922 applications, use the parameters listed in Table 1.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
Input voltage | 2.25 V to 2.75 V |
Output voltage | 1.8 V |
Output current | 2000 mA |
Output capacitor range | 22 µF to 47 µF |
Output capacitor ESR range | 2 mΩ to 500 mΩ |
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The LP5922 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input, output, and the noise-reduction pin (SS/NR). Multilayer ceramic capacitors have become the industry standard for these types of applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged because of large variations in capacitance. Additionally, the case size has a direct impact on the capacitance versus applied voltage derating.
Regardless of the ceramic capacitor type selected, the actual capacitance varies with the applied operating voltage and temperature. As a rule of thumb, derate ceramic capacitors by at least 50%. The input and output capacitors recommended herein account for a effective capacitance derating of approximately 50%, but at high applied voltage conditions the capacitance derating can be greater than 50% and must be taken into consideration. The minimum capacitance values declared in Input and Output Capacitors must be met across the entire expected operating voltage range and temperature range.
An input capacitor is required for stability. A capacitor with a value of at least 22 μF must be connected between the LP5922 IN pin and ground for stable operation over full load current range. It is acceptable to have more output capacitance than input, as long as the input is at least 22 μF.
The input capacitor must be located as close as possible to, but at a distance not more than 1 cm from, the IN pin and returned to the device GND pin with a clean analog ground. This will minimize the trace inductance between the capacitor and the device. Any good quality ceramic or tantalum capacitor may be used at the input.
The LP5922 is designed to work specifically with a low ESR ceramic (MLCC) output capacitor, typically 22 μF. A ceramic capacitor (dielectric types X5R or X7R) in the 22-μF to 100-μF range, with an ESR not exceeding 500 mΩ, is suitable in the LP5922 application circuit having an output voltage greater than 0.8 V. For output voltages of 0.8 V or less, the output capacitance must be increased to typically 47 μF. The output capacitor must be connected between the device OUT and GND pins. The output capacitor must meet the requirement for the minimum value of capacitance and have an ESR value that does not exceed 500 mΩ to ensure stability.
It is possible to use tantalum capacitors at the device output, but these are not as attractive for reasons of size, cost, and performance.
A combination of multiple output capacitors in parallel boosts the high-frequency PSRR. The combination of one 0805-sized, 47-µF ceramic capacitor in parallel with two 0805-sized, 10-µF ceramic capacitors with a sufficient voltage rating optimizes PSRR response in the frequency range of 400 kHz to 700 kHz (which is a typical range for dc-dc supply switching frequency). This 47-µF || 10-µF || 10-µF combination also ensures that at high input voltage and high output voltage configurations, the minimum effective capacitance is met. Many 0805-sized, 47-µF ceramic capacitors have a voltage derating of approximately 60% to 75% at 5 V, so the addition of the two 10-µF capacitors ensures that the capacitance is at or above 22 µF.
Recommended value for CSS/NR is 100 nF or larger. The soft-start period can be calculated by Equation 2. The CSS/NR capacitor is also the filter capacitor for internal reference for noise reduction purpose.
Although a feed-forward capacitor (CFF) from the FB pin to the OUT pin is not required to achieve stability, a 10-nF external CFF optimizes the transient, noise, and PSRR performance. A higher capacitance CFF value can be used; however, the start-up time may be longer and the Power-Good signal may incorrectly indicate that the output voltage is settled. The maximum recommended value is 100 nF
To ensure proper PGx functionality, the time constant defined by CNR/SSx must be greater than or equal to the time constant from CFFx. For a detailed description, see the application report Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator (SBVA042).
The LP5922 remains stable, and in regulation, with no external load.
Knowing the device power dissipation and proper sizing of the thermal plane connected to the exposed thermal pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 3.
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that is greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance.
On the WSON (DSC) package, the primary conduction path for heat is through the exposed thermal pad into the PCB. To ensure the device does not overheat, connect the exposed thermal pad, through multiple thermal vias, to an internal ground plane with an appropriate amount of PCB copper area.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 4 or Equation 5:
If the VIN – VOUT voltage is known, the maximum allowable output current can be calculated with Equation 6
Unfortunately, the RθJA value is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the PCB size, total copper area, copper weight, any thermal vias, and location of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper spreading area, and is to be used only as a relative measure of package thermal performance. For a well designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and ΨJB) are given in the Thermal Information table and are used in accordance with Equation 7 and Equation 8.
where
where
For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal Metrics ; for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics ; and for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see the TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs. These application notes are available at www.ti.com.
The continuous operational area of an LDO is limited by the input voltage (VIN), the output voltage (VOUT), the dropout voltage (VDO), the output current (IOUT), and the junction temperature (TJ). The recommended area for continuous operation for a linear regulator can be separated into the following steps, and is shown in Figure 16.
Figure 17 to Figure 22 show the recommended continuous operating area boundaries for this device in the WSON (DSC) package mounted to a EIA/JEDEC High-K printed circuit board, as defined by JESD51-7, with an RθJA rating of 49.5°C/W.