SNVSAT1A September 2017 – June 2021 LP87332D-Q1
PRODUCTION DATA
If the regulator is disabled, because of protection or fault (short-circuit protection, overload protection, thermal shutdown, input overvoltage protection, or UVLO), then the output power FETs are set to high-impedance mode and the output pulldown resistor is enabled (if enabled with the BUCKx_RDIS_EN bit in the BUCKx_CTRL_1 register and the LDOx_RDIS_EN bit in the LDOx_CTRL register). The turnoff time of the output voltage is defined by the output capacitance, load current, and resistance of the integrated pull-down resistor. The pull-down resistors are active as long as the VANA voltage is above approximately a 1.2-V level.