SNVSAT1A September   2017  – June 2021 LP87332D-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
          3. 7.3.8.1.3 PGOOD Pin Inactive Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  LDO0_CTRL
        10. 7.6.1.10 LDO1_CTRL
        11. 7.6.1.11 LDO0_VOUT
        12. 7.6.1.12 LDO1_VOUT
        13. 7.6.1.13 BUCK0_DELAY
        14. 7.6.1.14 BUCK1_DELAY
        15. 7.6.1.15 LDO0_DELAY
        16. 7.6.1.16 LDO1_DELAY
        17. 7.6.1.17 GPO_DELAY
        18. 7.6.1.18 GPO2_DELAY
        19. 7.6.1.19 GPO_CTRL
        20. 7.6.1.20 CONFIG
        21. 7.6.1.21 PLL_CTRL
        22. 7.6.1.22 PGOOD_CTRL_1
        23. 7.6.1.23 PGOOD_CTRL_2
        24. 7.6.1.24 PG_FAULT
        25. 7.6.1.25 RESET
        26. 7.6.1.26 INT_TOP_1
        27. 7.6.1.27 INT_TOP_2
        28. 7.6.1.28 INT_BUCK
        29. 7.6.1.29 INT_LDO
        30. 7.6.1.30 TOP_STAT
        31. 7.6.1.31 BUCK_STAT
        32. 7.6.1.32 LDO_STAT
        33. 7.6.1.33 TOP_MASK_1
        34. 7.6.1.34 TOP_MASK_2
        35. 7.6.1.35 BUCK_MASK
        36. 7.6.1.36 LDO_MASK
        37. 7.6.1.37 SEL_I_LOAD
        38. 7.6.1.38 I_LOAD_2
        39. 7.6.1.39 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.8 Diagnosis and Protection Features

The LP87332D-Q1 is capable of providing four levels of protection features:

  • Information of valid regulator output voltage, which sets the interrupt or PGOOD signal.
  • Warnings for diagnosis, which sets the interrupt.
  • Protection events, which are disabling the regulators.
  • Faults, which are causing the device to shutdown.

The LP87332D-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. The nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in the INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, then the interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded from the OTP during reset sequence.

Table 7-4 Summary of Interrupt Signals
EVENTDEVICE RESPONSEINTERRUPT BITINTERRUPT MASK BITSTATUS BITRECOVERY AND INTERRUPT CLEAR
Buck current limit triggeredNo effectBUCK_INT
BUCKx_ILIM_INT		BUCKx_ILIM_MASKBUCKx_ILIM_STATWrite 1 to the BUCKx_ILIM_INT bit.
Interrupt is not cleared if the current limit is active
LDO current limit triggeredNo effectLDO_INT
LDOx_ILIM_INT		LDOx_ILIM_MASKLDOx_ILIM_STATWrite 1 to the LDOx_ILIM_INT bit
Interrupt is not cleared if the current limit is active
Buck short circuit (VVOUT < 0.35 V at 1 ms after enable) or overload (VVOUT decreasing below 0.35 V during operation, 1-ms debounce)Regulator disableBUCK_INT
BUCKx_SC_INT		N/AN/AWrite 1 to the BUCKx_SC_INT bit
LDO short circuit (VVOUT < 0.3 V at 1 ms after enable) or overload (VVOUT decreasing below 0.3 V during operation, 1-ms debounce)Regulator disableLDO_INT
LDOx_SC_INT		N/AN/AWrite 1 to the LDOx_SC_INT bit
Thermal warningNo effectTDIE_WARN_INTTDIE_WARN_MASKTDIE_WARN_STATWrite 1 to tge TDIE_WARN_INT bit
Interrupt is not cleared if the temperature is above the thermal warning level
Thermal shutdownAll the regulators are disabled immediately, and the GPO and GPO2 are set to lowTDIE_SD_INTN/ATDIE_SD_STATWrite 1 to the TDIE_SD_INT bit
Interrupt is not cleared if the temperature is above the thermal shutdown level
VANA overvoltage (VANAOVP)All the regulators are disabled immediately, and the GPO and GPO2 are set to lowOVP_INTN/AOVP_STATWrite 1 to the OVP_INT bit
Interrupt is not cleared if the VANA voltage is above the VANAOVP level
Buck power good, output voltage becomes validNo effectBUCK_INT
BUCKx_PG_INT		BUCKx_PGR_MASKBUCKx_PG_STATWrite 1 to the BUCKx_PG_INT bit
Buck power good, output voltage becomes invalidNo effectBUCK_INT
BUCKx_PG_INT		BUCKx_PGF_MASKBUCKx_PG_STATWrite 1 to the BUCKx_PG_INT bit
LDO Power good, output voltage becomes validNo effectLDO_INT
LDOx_PG_INT		LDOx_PGR_MASKLDOx_PG_STATWrite 1 to the LDOx_PG_INT bit
LDO power good, output voltage becomes invalidNo effectLDO_INT
LDOx_PG_INT		LDOx_PGF_MASKLDOx_PG_STATWrite 1 to the LDOx_PG_INT bit
PGOOD pin changing from active to inactive state(1)No effectPGOOD_INTPGOOD_MASKPGOOD_STATWrite 1 to the PGOOD_INT bit
External clock appears or disappearsNo effect to regulatorsSYNC_CLK_INT(2)SYNC_CLK_MASKSYNC_CLK_STATWrite 1 to the SYNC_CLK_INT bit
Load current measurement is readyNo effectI_MEAS_INTI_MEAS_MASKN/AWrite 1 to the I_MEAS_INT bit
Supply voltage VANAUVLO triggered (VANA falling)Immediate shutdown and the registers reset to default valuesN/AN/AN/AN/A
Supply voltage VANAUVLO triggered (VANA rising)Startup and the registers reset to default values and the OTP bits are loadedRESET_REG_INTRESET_REG_MASKN/AWrite 1 to the RESET_REG_INT bit
Software requested resetImmediate shutdown is followed by power up and the registers are reset to their default valuesRESET_REG_INTRESET_REG_MASKN/AWrite 1 to the RESET_REG_INT bit
(1) The PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. The PGOOD_POL bit in the PGOOD_CTRL_1 register affects only the PGOOD pin polarity, not the Power Good and PGOOD_INT interrupt polarity.
(2) If the clock is not available when the clock detector is enabled, then an interrupt is generated during the clock-dector operation.