SNVSBA3 December 2020 LP875761-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The LP875761-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers, their addresses, and their abbreviations are listed in Table 7-1. A more detailed description is given in Section 7.6.1.2 through Section 7.6.1.34.
This register map describes the default values for bits which are not read from OTP memory. The orderable code and the default register bit values are defined in part number specific Technical Reference Manual.