SNVSBA3 December 2020 LP875761-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Address: 0x24
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
Reserved | BUCK3_PG _MASK |
Reserved | BUCK3_ILIM _MASK |
Reserved | BUCK2_PG _MASK |
Reserved | BUCK2_ILIM _MASK |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7 | Reserved | R/W | 0h | |
6 | BUCK3_PG_MASK | R/W | X | Masking for the BUCK3 power-good
interrupt (the BUCK3_PG_INT bit in the INT_BUCK_2_3 register) This bit does not affect the BUCK3_PG_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
5 | Reserved | R | 0h | |
4 | BUCK3_ILIM_MASK | R/W | X | Masking for the BUCK3
current-limit-detection interrupt (the BUCK3_ILIM_INT bit in the
INT_BUCK_2_3 register) This bit does not affect the BUCK3_ILIM_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
3 | Reserved | R/W | 0h | |
2 | BUCK2_PG_MASK | R/W | X | Masking for the BUCK2 power-good
interrupt (the BUCK2_PG_INT bit in the INT_BUCK_2_3 register) This bit does not affect the BUCK2_PG_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |
1 | Reserved | R | 0h | |
0 | BUCK2_ILIM_MASK | R/W | X | Masking for the BUCK2 current
limit-detection interrupt (the BUCK2_ILIM_INT bit in the
INT_BUCK_2_3 register) This bit does not affect the BUCK2_ILIM_STAT status bit in the BUCK_2_3_STAT register. 0h = Interrupt generated 1h = Interrupt not generated |