SNVSBA3 December 2020 LP875761-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The LP875761-Q1 device supports start-up and shutdown sequencing with programmable delay for the regulator output using one EN1, EN2, or EN3 control signal. The regulator is selected for delayed control with:
There are four time steps available for start-up and shutdown sequences. The delay times are selected with DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in Table 7-4.
0_STARTUP_DELAY or 0_SHUTDOWN_DELAY | DOUBLE_DELAY = 0h HALF_DELAY = 1h | DOUBLE_DELAY = 1h HALF_DELAY = 1h | DOUBLE_DELAY = 0h HALF_DELAY = 0h | DOUBLE_DELAY = 1h HALF_DELAY = 0h |
---|---|---|---|---|
0h | 0 ms | 0 ms | 0 ms | 0 ms |
1h | 0.32 ms | 0.64 ms | 1 ms | 2 ms |
2h | 0.64 ms | 1.28 ms | 2 ms | 4 ms |
3h | 0.96 ms | 1.92 ms | 3 ms | 6 ms |
4h | 1.28 ms | 2.56 ms | 4 ms | 8 ms |
5h | 1.6 ms | 3.2 ms | 5 ms | 10 ms |
6h | 1.92 ms | 3.84 ms | 6 ms | 12 ms |
7h | 2.24 ms | 4.48 ms | 7 ms | 14 ms |
8h | 2.56 ms | 5.12 ms | 8 ms | 16 ms |
9h | 2.88 ms | 5.76 ms | 9 ms | 18 ms |
Ah | 3.2 ms | 6.4 ms | 10 ms | 20 ms |
Bh | 3.52 ms | 7.04 ms | 11 ms | 22 ms |
Ch | 3.84 ms | 7.68 ms | 12 ms | 24 ms |
dh | 4.16 ms | 8.32 ms | 13 ms | 26 ms |
Eh | 4.48 ms | 8.96 ms | 14 ms | 28 ms |
Fh | 4.8 ms | 9.6 ms | 15 ms | 30 ms |
An example of start-up and shutdown sequences is shown in Figure 7-6 and Figure 7-7. The start-up and shutdown delays for the master buck regulator BUCK0 regulator is 1 ms and 4 ms . The delay settings are used only for enable or disable control with EN1, EN2, and EN3 signals.