SNVSBA3 December 2020 LP875761-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
One or more regulators can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for enable and disable the regulators:
If the EN1, EN2, EN3 control pins are used for enable and disable then the control pin is selected with BUCK0_EN_PIN_SELECT[1:0] bits (in BUCK0_CTRL1 register). The delay from the control signal rising edge to enabling of the regulator is set by BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to disabling of the regulator is set by BUCK0_SHUTDOWN_DELAY[3:0] bits in BUCK0_DELAY register. The delays are valid only for EN1, EN2, EN3 signal control. The control with EN_BUCK0 bit is immediate without the delays.
The control of the regulator (with 0-ms delays) is shown in Table 7-3.
The control of the regulator cannot be changed from one ENx pin to a different ENx pin because the control is ENx signal edge sensitive. The control from ENx pin to register bit and back to the original ENx pin can be done during operation.
CONTROL METHOD | EN_BUCK0 | EN_PIN_CTRL0 | BUCK0_EN_PIN_SELECT[1:0] | EN1 PIN | EN2 PIN | EN3 PIN | BUCKx OUTPUT VOLTAGE | |
---|---|---|---|---|---|---|---|---|
Enable and disable control with EN_BUCK0 bit | 0h | Don't Care | Don't Care | Don't Care | Don't Care | Don't Care | Disabled | |
1h | 0h | Don't Care | Don't Care | Don't Care | Don't Care | 1.0 Volt | ||
Enable and disable control with EN1 pin | 1h | 1h | 0h | Low | Don't Care | Don't Care | Disabled | |
1h | 1h | 0h | High | Don't Care | Don't Care | 1.0 Volt | ||
Enable and disable control with EN2 pin | 1h | 1h | 1h | Don't Care | Low | Don't Care | Disabled | |
1h | 1h | 1h | Don't Care | High | Don't Care | 1.0 Volt | ||
Enable and disable control with EN3 pin | 1h | 1h | 2h | Don't Care | Don't Care | Low | Disabled | |
1h | 1h | 2h | Don't Care | Don't Care | High | 1.0 Volt |
The regulator is enabled by the ENx pin or by I2C writing as shown in Figure 7-5. The soft-start circuit limits the in-rush current during start-up. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate controlled . If there is a short circuit at the output and the output voltage does not increase above 0.35-V level in 1 ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the Power-Good threshold level the BUCKx_PG_INT interrupt flag (in INT_BUCK_x register) is set. The Power-Good interrupt flag can be masked using BUCKx_PG_MASK bit (in BUCKx_MASK register).
The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default, and the host can disable those with ENx_PD bits (in CONFIG register).