LP8758-E3 Four 4-A Output Synchronous Step-Down DCDC Converters

1 Features

Fully Integrated Quad Buck, up to 4-A Programmable Maximum Output Current Per Buck
- Auto PWM-PFM and Forced-PWM Operations
- Programmable Output Voltage Slew Rate From 30 mV/µs to 0.5 mV/µs
- Input Voltage Range: 2.5 V to 5.5 V
- V_OUT Range: 0.5 V to 3.36 V with DVS
Programmable Start-Up and Shutdown Sequencing With Enable Signal
I²C-Compatible Interface That Supports Standard (100 kHz), Fast (400 kHz),
Fast+ (1 MHz), and High-Speed (3.4 MHz) Modes
Interrupt Function with Programmable Masking
Load Current Measurement
Output Short-Circuit and Overload Protection
Spread-Spectrum Mode for EMI Reduction
The Four Buck Cores Operate 90° out of Phase Thereby Reducing Input Ripple Current
Overtemperature Warning and Protection
Undervoltage Lockout (UVLO)

2 Applications

3 Description

The LP8758-E3 device is designed to meet power management requirements for low-power processors in mobile phones, network cards, and similar applications. The device contains four step-down DC-DC converter cores, providing four output voltage rails. The device is controlled by an I²C-compatible serial interface.

The automatic PWM-PFM (AUTO mode) operation maximizes efficiency over a wide output-current range.

The LP8758-E3 supports programmable start-up and shutdown sequencing synchronized to hardware Enable input signal.

The protection features include short-circuit protection, current limits, input supply UVLO, and temperature warning and shutdown functions. Several error flags are provided for status information of the device. In addition, the LP8758-E3 device supports load current measurement without the addition of external current sense resistors. During start-up and voltage change, the device controls the output slew rate to minimize output voltage overshoot and the inrush current.

For all available packages, see the orderable addendum at the end of the data sheet.

Device Images

Simplified Schematic

Efficiency vs Output Current

V_OUT settings = 1.8 V and 2.5 V

4 Revision History

DATE	REVISION	NOTES
February 2020	*	Initial Release

5 Pin Configuration and Functions

YFF Package

35-Pin DSBGA

Top View

YFF Package

35-Pin DSBGA

Bottom View

Pin Functions

PIN		TYPE	DESCRIPTION
NUMBER	NAME	TYPE	DESCRIPTION
A1, B1	VIN_B1	P	Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed.
A2, B2	SW_B1	A	Buck1 switch node.
A3, B3, C3	PGND_B01	G	Power Ground for Buck0 and Buck1.
A4, B4	SW_B0	A	Buck0 switch node.
A5, B5	VIN_B0	P	Input for Buck0. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed.
C1	SGND	G	Substrate Ground.
C2	FB_B1	A	Output voltage feedback for Buck1.
C4	FB_B0	A	Output voltage feedback for Buck0.
C5	EN1	D/I	Programmable Enable signal for Buck converter core or cores. Can be also configured to switch between two output voltage levels.
D1	AGND	G	Ground.
D2	nINT	D/O	Open-drain interrupt output. Active LOW.
D3	EN2	D/I	Programmable Enable signal for Buck converter one or more cores. Can be also configured to switch between two output voltage levels.
D4	NRST	D/I	Reset signal for the device. Can be also used to enable the regulator.
D5	SDA	D/I/O	Serial interface data input and output for system access. Connect a pullup resistor.
E1	VANA	P	Supply voltage for Analog and Digital blocks.
E2	FB_B3	A	Output voltage feedback for Buck3.
E4	FB_B2	A	Output voltage feedback for Buck2.
E5	SCL	D/I	Serial interface clock input for system access. Connect a pullup resistor.
F1, G1	VIN_B3	P	Input for Buck3. The separate power pins VIN_Bx are not connected together internally – VIN_Bx pins must be connected together in the application and be locally bypassed.
F2, G2	SW_B3	A	Buck3 switch node.
E3, F3, G3	PGND_B23	G	Power Ground for Buck2 and Buck3.
F4, G4	SW_B2	A	Buck2 switch node.
F5, G5	VIN_B2	P	Input for Buck2. The separate power pins VIN_Bx are not connected together internally - VIN_Bx pins must be connected together in the application and be locally bypassed.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
INPUT VOLTAGE
VIN_Bx, VANA	Voltage on power connections	–0.3	6	V
SW_Bx	Voltage on buck switch nodes	–0.3	(VIN_Bx + 0.3 V) with 6 V maximum	V
FB_Bx	Voltage on buck voltage sense nodes	–0.3	(VANA + 0.3 V) with 6 V maximum	V
NRST	Voltage on NRST input	–0.3	3.6	V
ENx, SDA, SCL, nINT	Voltage on logic pins (input or output pins)	–0.3	3.6	V
CURRENT
VIN_Bx, SW_Bx, PGND_Bx	Current on power pins (average current over 100k hour lifetime, T_J = 125°C)		0.62	A/pin
TEMPERATURE
T_J-MAX	Junction temperature	−40	150	°C
Maximum lead temperature (soldering, 10 seconds)⁽³⁾			260	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground.

(3) For detailed soldering specifications and information, please refer to DSBGA Wafer Level Chip Scale Package.