SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
The LP876242-Q1 device monitors the undervoltage (UV) and overvoltage (OV) conditions on the output voltages of the BUCK regulators, the UV and OV conditions on the VMONn voltage monitoring input pins , and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication. This selection is set by the PGOOD_SEL_BUCKn register bits for each BUCK regulator (select primary phase for multi-phase regulator). When voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal.
The PGOOD signal represents the momentary status of the included indications without latching. If the PGOOD signal goes low due to an indicated warning or error condition, the PGOOD signal goes high immediately when the previous indicated warning or error condition is no longer present.
The BUCKn_VMON_EN bit enables the overvoltage (OV) , undervoltage (UV) and short-circuit (SC) comparators. The current limit (ILIM) comparator of each BUCK regulator is activated as soon as the corresponding BUCK regulator is enabled. In order to add the current limit indication of a BUCK regulator to the PGOOD signal, the BUCKn_VMON_EN bit of the corresponding BUCK regulator must be set. When a BUCK is not needed as a regulated output, it can be used as a voltage monitor for an external rail. For BUCK converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as a voltage monitor for an external rail that is connected to the FB_Bn pin of the BUCK regulator.
When the voltage monitor for a BUCK regulator is disabled, the output of the corresponding monitor is automatically masked to prevent it from forcing PGOOD inactive. The masking allows PGOOD to be connected to other open-drain power good signals in the system.
The VCCA input voltage monitoring is enabled with VCCA_VMON_EN bit. The monitoring can be enabled by an NVM default setting, that starts the monitoring of the VCCA voltage after the voltage monitor passes ABIST during the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA monitor is included in the