SNVSAL1C December   2017  – June 2021 LP87702-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. 8.3.6.1 Enabling and Disabling Converters
        2. 8.3.6.2 Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. 8.3.10.1 Voltage Monitorings
        2. 8.3.10.2 Interrupts
        3. 8.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 8.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 8.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 8.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 8.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 8.3.10.4.1 Output Power Limit
          2. 8.3.10.4.2 Thermal Warning
        5. 8.3.10.5 Protections Causing Converter Disable
          1. 8.3.10.5.1 Short-Circuit and Overload Protection
          2. 8.3.10.5.2 Overvoltage Protection
          3. 8.3.10.5.3 Thermal Shutdown
        6. 8.3.10.6 Protections Causing Device Power Down
          1. 8.3.10.6.1 Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 LP8770_map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Buck Input Capacitor Selection
          3. 9.2.2.1.3 Buck Output Capacitor Selection
          4. 9.2.2.1.4 Boost Input Capacitor Selection
          5. 9.2.2.1.5 Boost Output Capacitor Selection
          6. 9.2.2.1.6 Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.10.2 Interrupts

The LP87702-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. The nINT output pin is driven high after all the flag bits and pending interrupts are cleared.

Fault detection is indicated by the RESET_REG_INT interrupt flag bit set in the INT_TOP_2 register after the start-up event.

Table 8-5 Summary of Interrupt Signals
EVENT SAFE STATE INTERRUPT BIT INTERRUPT MASK STATUS BIT RECOVERY/INTERRUPT CLEAR
Buck current limit triggered (20-µs debounce) No effect BUCK_INT = 1
BUCKx_ILIM_INT = 1		 BUCKx_ILIM_MASK BUCKx_ILIM_STAT Write 1 to the BUCKx_ILIM_INT bit
Interrupt is not cleared if the current limit is active.
Boost current limit triggered No effect BOOST_INT = 1
BOOST_ILIM_INT = 1		 BOOST_ILIM_MASK BOOST_ILIM_STAT Write 1 to the BOOST_ILIM_INT bit.
Interrupt is not cleared if the current limit is active.
Buck short circuit (VVOUT < 0.35V at 1 ms after enable) or Overload (VVOUT decreasing below 0.35 V during operation, 1 ms debounce) Converter disable BUCKx_INT = 1
BUCKx_SC_INT = 1		 N/A N/A Write 1 to the BUCKx_SC_INT bit.
Boost short circuit Converter disable BOOST_INT = 1
BOOST_SC_INT = 1		 N/A N/A Write 1 to the BOOST_SC_INT bit.
Thermal warning No effect TDIE_WARN_INT) = 1 TDIE_WARN_MASK TDIE_WARN_STAT Write 1 to the TDIE_WARN_INT bit.
Interrupt is not cleared if the temperature is above the thermal warning level.
Thermal shutdown All converters disabled immediately and GPOx set to low TDIE_SD_INT = 1 N/A TDIE_SD_STAT Write 1 to TDIE_SD_INT bit
Interrupt is not cleared if temperature is above thermal shutdown level
VANA overvoltage (VANAOVP) All converters disabled immediately and GPOx set to low OVP_INT N/A OVP_STAT Write 1 to the OVP_INT bit.
Interrupt is not cleared if the VANA voltage is above the VANAOVP level.
Buck power-good, output voltage becomes valid. No effect BUCK_INT = 1
BUCKx_PG_INT = 1		 BUCKx_PGR_MASK BUCKx_PG_STAT Write 1 to the BUCKx_PG_INT bit.
Buck power-good, output voltage becomes invalid No effect BUCK_INT = 1
BUCKx_PG_INT = 1		 BUCKx_PGF_MASK BUCKx_PG_STAT Write 1 to the BUCKx_PG_INT bit.
Boost power-good, output voltage becomes valid. No effect BOOST_INT = 1
BOOST_PG_INT = 1		 BOOST_PGR_MASK BOOST_PG_STAT Write 1 to the BOOST_PG_INT bit.
Boost power-good, output voltage becomes invalid. No effect BOOST_INT = 1
BOOST_PG_INT = 1		 BOOST_PGF_MASK BOOST_PG_STAT Write 1 to the BOOST_PG_INT bit.
VMON1 power-good, input voltage becomes valid. No effect DIAG_INT = 1
VMON1_PG_INT = 1		 VMON1_PGR_MASK VMON1_PG_STAT Write 1 to the VMON1_PG_INT bit.
VMON1 power-good, input voltage becomes invalid. No effect DIAG_INT = 1
VMON1_PG_INT = 1		 VMON1_PGF_MASK VMON1_PG_STAT Write 1 to the VMON1_PG_INT bit.
VMON2 power-good, input voltage becomes valid. No effect DIAG_INT = 1
VMON2_PG_INT = 1		 VMON2_PGR_MASK VMON2_PG_STAT Write 1 to the VMON2_PG_INT bit.
VMON2 power-good, input voltage becomes invalid. No effect DIAG_INT = 1
VMON2_PG_INT = 1		 VMON2_PGF_MASK VMON2_PG_STAT Write 1 to the VMON2_PG_INT bit.
VANA power-good, input voltage becomes valid. No effect DIAG_INT = 1
VANA_PG_INT = 1		 VANA_PGR_MASK VANA_PG_STAT Write 1 to the VANA_PG_INT bit.
VANA power-good, input voltage becomes invalid. No effect DIAG_INT = 1
VANA_PG_INT = 1		 VANA_PGF_MASK VANA_PG_STAT Write 1 to the VANA_PG_INT bit.
External clock appears or disappears. No effect to converters SYNC_CLK_INT(1) SYNC_CLK_MASK SYNC_CLK_STAT Write 1 to the SYNC_CLK_INT bit.
Load current measurement ready No effect I_MEAS_INT = 1 I_MEAS_MASK N/A Write 1 to the I_MEAS_INT bit.
Supply voltage VANAUVLO triggered (VANA falling) Immediate shutdown, registers reset to default values N/A N/A N/A N/A
Supply voltage VANAUVLO triggered (VANA rising) Start-up, registers reset to default values and OTP bits loaded RESET_REG_INT = 1 RESET_REG_MASK N/A Write 1 to the RESET_REG_INT bit.
Software requested reset Immediate shutdown followed by powerup, registers reset to default values RESET_REG_INT = 1 RESET_REG_MASK N/A Write 1 to the RESET_REG_INT bit.
(1) Interrupt generated during the Clock Detector operation and in case the Clock is not available when the Clock Detector is enabled.