SNVSAL1C December   2017  – June 2021 LP87702-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Serial Bus Timing Parameters
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Descriptions
      1. 8.3.1  Step-Down DC/DC Converters
        1. 8.3.1.1 Overview
        2. 8.3.1.2 Transition Between PWM and PFM Modes
        3. 8.3.1.3 Buck Converter Load Current Measurement
      2. 8.3.2  Boost Converter
      3. 8.3.3  Spread-Spectrum Mode
      4. 8.3.4  Sync Clock Functionality
      5. 8.3.5  Power-Up
      6. 8.3.6  Buck and Boost Control
        1. 8.3.6.1 Enabling and Disabling Converters
        2. 8.3.6.2 Changing Buck Output Voltage
      7. 8.3.7  Enable and Disable Sequences
      8. 8.3.8  Window Watchdog
      9. 8.3.9  Device Reset Scenarios
      10. 8.3.10 Diagnostics and Protection Features
        1. 8.3.10.1 Voltage Monitorings
        2. 8.3.10.2 Interrupts
        3. 8.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins
          1. 8.3.10.3.1 PGx Pin Gated (Unusual) Mode
          2. 8.3.10.3.2 PGx Pin Operation in Continuous Mode
          3. 8.3.10.3.3 Summary of PG0, PG1 Gated, and Continuous Operating Modes
        4. 8.3.10.4 Warning Interrupts for System Level Diagnostics
          1. 8.3.10.4.1 Output Power Limit
          2. 8.3.10.4.2 Thermal Warning
        5. 8.3.10.5 Protections Causing Converter Disable
          1. 8.3.10.5.1 Short-Circuit and Overload Protection
          2. 8.3.10.5.2 Overvoltage Protection
          3. 8.3.10.5.3 Thermal Shutdown
        6. 8.3.10.6 Protections Causing Device Power Down
          1. 8.3.10.6.1 Undervoltage Lockout
      11. 8.3.11 OTP Error Correction
      12. 8.3.12 Operation of GPO Signals
      13. 8.3.13 Digital Signal Filtering
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Interface
        1. 8.5.1.1 Data Validity
        2. 8.5.1.2 Start and Stop Conditions
        3. 8.5.1.3 Transferring Data
        4. 8.5.1.4 I2C-Compatible Chip Address
        5. 8.5.1.5 Auto Increment Feature
    6. 8.6 Register Maps
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 LP8770_map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Application Components
          1. 9.2.2.1.1 Inductor Selection
          2. 9.2.2.1.2 Buck Input Capacitor Selection
          3. 9.2.2.1.3 Buck Output Capacitor Selection
          4. 9.2.2.1.4 Boost Input Capacitor Selection
          5. 9.2.2.1.5 Boost Output Capacitor Selection
          6. 9.2.2.1.6 Supply Filtering Components
      3. 9.2.3 Current Limit vs Maximum Output Current
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.8 Window Watchdog

Figure 8-8 shows the LP87702-Q1 watchdog's operation (for an example, when the ENx pin is used for controlling power sequence and ENx pin is active).

WDI is the watchdog function input pin, and WD_RESET is the reset output. The WDI pin needs pulsed within a certain timing window to avoid a watchdog expiration. The minimum pulse width is 100 µs. The watchdog expiration always causes a reset pulse at WD_RESET output, otherwise the device behavior after watchdog expiration is programmable. WD_RESET output polarity and mode, push-pull or open drain, are also programmable.

Watchdog default settings are read from OTP during device start-up. Default settings in WD_CTRL_1 and WD_CTRL_2 register can be over-written through the I2C (as long as WD_LOCK bit is not set to 1). Writing WD_LOCK = 1 in WD_CTRL_2 register locks watchdog settings until NRST input is driven low, power cycle or register reset by SW_RESET.

Table 8-4 shows how the long open, close, and open window periods are independently programmable. The watchdog enters the WD Reset state when the long open or open window expires before the WDI input is received. Also, the watchdog enters the WD Reset when the WDI is received during close window. Long open period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register; the register access initializes the long open counter and the long open period restarts (except in Stop mode).

LP87702-Q1 behavior after WD expiration is programmable:

  • When WD_RESET_CNTR_SEL = 00, system restart is disabled and converters are maintained ON. WD_RESET pin is active for 10 ms. Watchdog returns to Long Open mode.
  • When WD_RESET_CNTR_SEL = 01 (restart after first reset pulse), LP87702-Q1 performs shutdown sequence followed by start-up sequence so the converters are disabled and re-enabled according to the OTP programmed sequences. The device reloads OTP defaults when WD_EN_OTP_READ = 1 during start-up. Settings valid before shutdown are maintained when the WD_EN_OTP_READ = 0. WD_RESET output pin is active for a period of (10 ms + maximum shutdown delay). Maximum shutdown delay can be selected as 7.5 ms (SHUTDOWN_DELAY_SEL = 0) or 15 ms (SHUTDOWN_DELAY_SEL = 1). After the restart watchdog returns to Long Open mode.
  • The status bit (WD_SYSTEM_RESTART_FLAG) is set to indicate that a system restart has happened. The status can be cleared by writing 1 to WD_CLR_SYSTEM_RESTART_FLAG. WD_RESET_CNTR_SEL can be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. The current status of the reset counter is available in WD_RESET_CNTR_STATUS.(1) The reset counter can be cleared by writing WD_CLR_RESET_CNTR to 1.
  • Watchdog can also be programmed to perform shutdown sequence and enter STOP mode after the second WD expiration. In STOP mode converters are OFF. WD_RESET output pin is activated for a period of (10 ms + maximum shutdown delay), in STOP mode WD_RESET is inactive. NRST, power cycle, register reset SW_RESET, writing WD_CLR_SYSTEM_RESTART_FLAG = 1 or writing WD_SYSTEM_RESTART_FLAG_MODE = 0 is required to recover. This WD operating mode is selected by setting OTP bit WD_SYS_RESTART_FLAG_MODE = 1.

Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting the WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.1

Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active. Watchdog behavior can be slightly different depending on the OTP settings and the ENx pin state, which follows:

  • When the ENx pin is used for controlling the power sequence and the ENx pin is not active, the shutdown sequence cannot be performed. WD_RESET pulse length is fixed 31 ms.
  • There is no OTP defined power sequence when the ENx pins are not used for power sequence control, and all converters and GPOs are enabled through the I2C. WD expiration does not cause a converter disable or enable sequence even when the OTP settings for the watchdog enable restart. In this case WD_RESET pulse is 11 ms.

GUID-DDBE670B-7B20-45E6-BDE5-594BD05E0488-low.gif Figure 8-8 Watchdog Operation
Table 8-4 Watchdog Window Periods
CONTROL BITDEFAULTVALUES
WD_LONG_OPEN_TIMEOTP00 – 200 ms
01 – 600 ms
10 – 2000 ms
11 – 5000 ms
WD_CLOSE_TIMEOTP00 – 10 ms
01 – 20 ms
10 – 50 ms
11 – 100 ms
WD_OPEN_TIMEOTP00 – 20 ms
01 – 100 ms
10 – 600 ms
11 – 2000 ms

LP87702-Q1 supports option to disable watchdog. WD_DIS pin function is multiplexed with CLKIN/GPIO2 functions. Watchdog disable option can be selected by setting register bit WD_DIS_CTRL = 1. When WD_DIS_CTRL = 1, WD is disabled if CLKIN/GPIO2/WD_DIS pin is HIGH and enabled if CLKIN/GPIO2/WD_DIS pin is LOW. If WD_DIS_CTRL is toggled to disable and re-enable WD, WD starts from Long Open window after re-enabling.

Default for WD_DIS_CTRL is set in OTP. WD_DIS_CTRL value can be changed via I2C until WD settings are locked. When WD_LOCK is set to 1, WD is enabled regardless of WD_DIS_CTRL value. WD_DIS_CTRL bit is protected by write lock. Three consecutive codes have to be written to WD_DIS_UNLOCK_CODE to open WD_DIS_CTRL for write access.

1. WD_RESET_CNTR_STATUS is valid only when WD_RESET_CNTR_SEL is set to either 00 or 03.