8.1.1 Boost Controller

The boost controller generates a 16-V to 48-V supply for LED strings. To optimize LED drive efficiency the boost controller includes adaptive output voltage control which gets feedback from monitoring the internal LED current sinks voltage circuit. This feature minimizes power consumption by adjusting the boost voltage to lowest sufficient level in all conditions.

Boost switching frequency can be set in a wide range from 100 kHz to 2.2 MHz. This enables system optimization for both high power applications, where efficiency is critical, and for lower power applications where small solution size can be achieved with high boost switching frequency.

The LP8860-Q1 has several features for system EMI optimization:

• Boost switching frequency can be selected either below or above AM band.
• Spread spectrum can be enabled to reduce energy around the switching frequency and its harmonics.
• Boost switching can be synchronized to an external clock with a dedicated SYNC input.
• Gate drive strength for the external FET is controllable with EEPROM.

8.1.2 LED Output Configurations

The LP8860-Q1 has four high-precision current sinks with up to 150 mA per output capability. LED outputs can be connected parallel to reach higher current levels.

LED outputs are highly configurable; for example, there are features such as brightness slope control, external clock synchronization, phase shifting, adaptive headroom control, etc.

In general there are 2 main user modes:

• Display Mode (with full feature set) and/or
• Cluster Mode (with limited feature set)

These modes and features are detailed in later sections.

8.1.3 Display Mode

In Display Mode LED outputs are configured to power an LCD backlight. Maximum current per string is set by R_ISET; alternatively, through a user-programmable EEPROM value.

Brightness is controlled with PWM input or I²C/SPI register writes. An optional sloper feature enables automatic smooth transition between brightness levels. Sloper time can be programmed to EEPROM registers, and an advanced slope feature allows smoother response to eye compared to traditional linear slope.

Outputs are controlled with a Phase Shift PWM (PSPWM) Scheme. Due to the phase shift between the outputs they are not activated simultaneously which brings several benefits:

• Peak load current from the boost output is decreased, which reduces the voltage ripple seen at the boost output and allows smaller output capacitors.
• Smaller ripple reduces the possible audible noise from the ceramic boost output capacitors.
• PSPWM scheme multiplies the effective load frequency seen at the boost output by number of active channels. This further reduces the audible noise by transferring the output ripple frequency above human hearing.
• Optical ripple through LCD panel is reduced, helping to reduce the “waterfall” effect which is caused by asynchronous backlight ripple and LCD refresh.

PWM output frequency is set with EEPROM registers from 4.9 kHz to 39 kHz. Selecting output frequency depends on the number of strings used, system requirements for the frequency, and desired dimming ratio. Dimming resolution is a function of PWM output frequency — the higher the frequency, the lower the resolution.

User can choose to increase resolution by:

• enabling dithering function (optional through EEPROM), or
• increasing internal clock frequency.

Increasing internal clock frequency increases device current consumption.

In high-quality display systems an "anti-waterfall" feature may be required. The LP8860-Q1 supports this by offering output synchronization to the LCD refresh signal through VSYNC input. VSYNC input is synchronized to outputs through internal PLL; EEPROM and filtering are described in later sections.

8.1.4 Cluster Mode

In Cluster mode LED strings have independent control but fewer features enabled than in Display Mode.

Brightness (PWM and current) are independently controlled for all 4 outputs. When there is an unequal number of LEDs per channel, the LP8860-Q1 adaptive voltage control is not used in Cluster mode; therefore, boost output voltage is fixed (or externally controlled or powered).

In Cluster mode PWM frequency can be set through EEPROM, and Phase Shift PWM mode is enabled.

Cluster mode does not support the PWM input pin, hybrid dimming, slope control or dither mode.

8.1.5 Hybrid Dimming

Hybrid dimming combines both PWM and current-dimming benefits offering the best optical efficiency to drive LEDs. At higher brightness levels only the LED constant current is controlled; at lower brightness levels LED brightness is controlled by adding PWM on top of low constant current value.

Because LED optical efficacy declines with high forward current, reducing the current yields better system optical efficiency compared with conventional PWM dimming. An additional benefit of current dimming is reduced EMI compared to PWM switching. PWM dimming is used with lower brightness values to achieve a higher dimming ratio. The optimum switch point between PWM and current dimming is programmable and depends on the LED type.

8.1.6 Charge Pump and Square Waveform (SQW) Output

The gate driver for the external boost FET can be powered directly from the VDD input or from the charge pump integrated into the LP8860-Q1. When a 5-V rail is available in the system for VDD supply, it is typically a high enough voltage to drive the external FET, and the internal charge pump can be disabled. In this case, the VDD and CPUMP pins must be shorted together, and the fly cap can be removed. When the system VDD is not high enough to drive the gate of the boost FET (typical case is 3.3 V), the charge pump can be used to multiply the gate drive voltage to 2× VDD.

The SQW output provides a 100-kHz square wave signal (1 mA maximum) with amplitude equal to the charge-pump output voltage. When the charge pump is disabled, the amplitude of the SQW signal is equal to VDD. See Charge Pump and High Output Voltage Application sections for usage examples.

8.1.7 Power-Line FET

Some automotive systems require a safety switch to disconnect the driver device from the battery. The LP8860-Q1 offers a power-line FET control circuit, which limits inrush current from the power line during start-up and reduces standby power consumption by disconnecting device from the power-line during an off state. This FET disconnects the boost and LED strings from the input during fault conditions. For example, when the input voltage is above the overvoltage protection (OVP) level, the power-line FET disconnects the LED strings from the power-line to protect LED outputs against overheating.

Depending on which fault has shut down the power-line FET, the device can enter automatic fault recovery state where the power-line FET is turned on in 100-ms time periods to see if the fault condition has been removed. If the fault was only short-term, and normal operation condition returns, the device turns back on automatically.

8.1.8 Protection Features

Extensive fault-detection and protection features of the LP8860-Q1 include:

• Open-string and shorted LED detections
  • LED fault detection prevents system overheating in case of open in some of the LED strings
• Boost overcurrent
• Boost overvoltage
• VIN input overvoltage protection
  • Threshold sensing from VSENSE_P pin
• VIN input undervoltage protection
  • Threshold sensing from VSENSE_P pin
• VIN input overcurrent protection
  • Threshold sensing across R_ISENSE resistor
• VDD input undervoltage lockout
• Thermal shutdown in case of die overtemperature (165°C nominal)

Fault protection thresholds are EEPROM programmable and some protection features can be disabled, or masked, if necessary.

A fault condition is indicated through the FAULT pin. If an I²C/SPI interface is used, the fault reason can be read from the register, and flags can be cleared with register write.

8.1.9 Advanced Thermal Protection Features

The LP8860-Q1 has a unique features for protecting against overheating:

1. Die temperature based Thermal de-rating function. Average LED current is automatically lowered when die temperature increases above a predefined (90ºC, 100ºC, or 110ºC) level. Decreasing LED current reduces thermal loading on the device and prevents overheating.
2. An external NTC sensor-based protection, where a sensor can be placed close to LEDs to protect them from overheating. The sensor is connected to the TSENSE pin of the device. Two methods are available:
   • Current de-rating, where the LED current is lowered proportionally to the temperature measured with the external NTC sensor. This method is available only if LED max current is set with R_ISET resistor.
   • Brightness limitation above a predefined temperature

8.3.1 Clock Generation

The LP8860-Q1 has an internal 10-MHz oscillator which is used for clocking the PWM input duty cycle measurement. The 10-MHz clock is divided by two, and the 5-MHz clock is used for clocking the state machine and internal timings.

The internal 5-MHz clock can be used for generating the LED PWM output frequency directly or it can be multiplied with an internal PLL to achieve higher resolution. The higher clock frequency for the PWM generation block allows the higher resolution; however, the tradeoff is higher power consumption of the part. Clock multiplication is set with <PWM_RESOLUTION[1:0]> EEPROM bits.

8.3.1.1 LED PWM Clock Generation With VSYNC

Unsynchronized LCD line scanning and LED backlight ripple may cause a “waterfall” effect. Synchronizating LED output PWM frequency with video processor or timing controller VSYNC/HSYNC signal can reduce this effect.

The PLL can be used for generating required PWM generation clock from the VSYNC signal. This ensures that the LED output PWM remains synchronized to the VSYNC signal, and there is no clock variation between the LCD display video update and the LED backlight output frequency. If PWM_COUNTER_RESET = 1, the VSYNC signal rising edge restartsthe PWM generation, ensuring there is no clock drifting. The slow divider is intended for LED PWM frequency synchronization with an external VSYNC. An external filter connected to the FILTER pin must be used only if a slow divider is enabled — otherwise the LP8860-Q1 uses internal compensation.

The ƒ_OUT of the PLL must be chosen in the 5-MHz to 40-MHz range. If VSYNC is enabled, the signal must be active before VDDIO/EN is set high and present whenever VDDIO/EN is high.

Figure 9. PLL Clock Generation

8.3.1.2 LED PWM Frequency and Resolution

LED output PWM frequency is selected with <PWM_FREQ[3:0]> EEPROM register when using a 5-MHz internal oscillator for generating PWM output. <LED_STRING_CONF[2:0]> bits define phase shift between LED outputs as described later. <PWM_RESOLUTION[1:0]> EEPROM bits select the PLL output frequency and hence the LED PWM resolution. PWM frequencies with <EN_SYNC> = 0 are listed in Table 1.

NOTE

If the VSYNC signal is used for generating PWM output frequency, it affects all clock frequencies, as well as the LED PWM output frequency. The EEPROM Bit Explanations section explains how all the dividers affect the output clocks.

Figure 10. PWM Clocking With Internal Oscillator

Figure 11. PWM Clocking With PLL, Internal Oscillator as Reference

Table 1. Output PWM Frequency and Resolution With Internal Oscillator

		00 OSC = 5 MHz	01 OSC = 10 MHz	10 OSC = 20 MHz	11 OSC = 40 MHz
PWM_FREQ[3:0]	PWM_RESOLUTION[1:0] PWM FREQUENCY (Hz)	RESOLUTION (bit)
1111	39063	7	8	9	10
1110	34180	7	8	9	10
1101	30518	7	8	9	10
1100	29297	7	8	9	10
1011	28076	7	8	9	10
1010	26855	7	8	9	10
1001	25635	7	8	9	10
1000	24412	7	8	9	10
0111	23192	7	8	9	10
0110	21973	7	8	9	10
0101	20752	7	8	9	10
0100	19531	8	9	10	11
0011	17090	8	9	10	11
0010	13428	8	9	10	11
0001	9766	9	10	11	12
0000	4883	10	11	12	13

Figure 12. PWM Synchronization With External VSYNC Input

PWM clock frequencies with different <SEL_DIVIDER>, <EN_PLL>, and <EN_SYNC> combinations are listed in Table 2.

Table 2. PLL Clock and LED PWM Frequency

PWM_SYNC	SEL_DIVIDER	EN_PLL	EN_SYNC	PLL CLOCK	PWM FREQUENCY
0	X	0	0	5 MHz	See Table 1
0	1	1	0	5, 10, 20, 40 MHz	See Table 1
0	0	1	1	SYNC × R_SEL[1:0] × SLOW_PLL_DIV[12:0]/ SYNC_PRE_DIV[3:0]	PLL clock / GEN_DIV
1	0	1	1	SYNC × GEN_DIV × SLOW_PLL_DIV[12:0]/ SYNC_PRE_DIV[3:0]	PLL clock / GEN_DIV

GEN_DIV coefficients and resolution (bit) are listed on Table 3.

Table 3. GEN_DIV Coefficients and Resolution

	PWM_RESOLUTION[1:0]
	00			01			10			11
PWM_ FREQ[3:0]	STEP	GEN_DIV	RES (bits)	STEP	GEN_DIV	RES (bits)	STEP	GEN_DIV	RES (bits)	STEP	GEN_DIV	RES (bits)
0000	64	1024.00	10	32	2048.00	11	16	4096.00	12	8	8192.00	13
0001	128	512.00	9	64	1024.00	10	32	2048.00	11	16	4096.00	12
0010	176	372.36	8	88	744.73	9	44	1489.45	10	22	2978.91	11
0011	224	292.57	8	112	585.14	9	56	1170.29	10	28	2340.57	11
0100	256	256.00	8	128	512.00	9	64	1024.00	10	32	2048.00	11
0101	272	240.94	7	136	481.88	8	68	963.76	9	34	1927.53	10
0110	288	227.56	7	144	455.11	8	72	910.22	9	36	1820.44	10
0111	304	215.58	7	152	431.16	8	76	862.32	9	38	1724.63	10
1000	320	204.80	7	160	409.60	8	80	819.20	9	40	1638.40	10
1001	336	195.05	7	168	390.10	8	84	780.19	9	42	1560.38	10
1010	352	186.18	7	176	372.36	8	88	744.73	9	44	1489.45	10
1011	368	178.09	7	184	356.17	8	92	712.35	9	46	1424.70	10
1100	384	170.67	7	192	341.33	8	96	682.67	9	48	1365.33	10
1101	400	163.84	7	200	327.68	8	100	655.36	9	50	1310.72	10
1110	448	146.29	7	224	292.57	8	112	585.14	9	56	1170.29	10
1111	512	128.00	7	256	256.00	8	128	512.00	9	64	1024.00	10

Dithering allows increased resolution and smaller average steps size. Dithering can be programmed with EEPROM bits <DITHER[2:0]> 0 to 4 bits. Figure 13 shows 1-bit dithering. For 3-bit dithering, every 8^th pulse is made 1 LSB longer to increase the average value by 1/8^th. Dither is available in steady state condition when <EN_STEADY_DITHER> is high, otherwise during slope only.

Figure 13. Example of the Dithering, 1-Bit Dither, 10-Bit Resolution

8.3.2 Brightness Control (Display Mode)

The LP8860-Q1 LED outputs can be configured to display or cluster mode. The following sections describe display mode options. Cluster mode is a special mode with individually controlled LED outputs. See Cluster Mode section for details.

The LP8860-Q1 controls the brightness of the display with conventional PWM or with Hybrid PWM and Current dimming. Brightness control is received either from PWM input pin or from I²C/SPI register bits. The brightness source is selected with <BRT_MODE[1:0]> bits as follows:

8.3.2.5 Brightness Slope

Sloper makes the smooth transition from one brightness value to another. Slope time can be programmed with EEPROM bits <PWM_SLOPE[2:0]> from 0 to 511 ms. Slope time is used for sloping up and down. Advanced slope makes brightness changes smooth for eye.

Table 5. Slope Time

PWM_SLOPE[2:0]	SLOPE TIME
000	disabled
001	1 ms
010	2 ms
011	52 ms
100	105 ms
101	210 ms
110	315 ms
111	511 ms

Figure 14. Sloper Operation

8.3.2.6 LED Dimming Methods

In additional to conventional PWM dimming control the LP8860-Q1 supports Hybrid PWM and Current dimming. Hybrid dimming combines the PWM and current dimming methods. PWM dimming operates with a lower range of light, and linear current dimming is used with higher brightness values. If the <EN_PWM_I EEPROM> bit is set to 1, the system enables hybrid dimming. Principles of PWM dimming and Hybrid PWM and Current dimming are illustrated by Figure 15. Only 25% switch points and slope gain = 1 are shown for simplicity.

Figure 15. Principles of PWM Dimming and Hybrid PWM and Current Dimming

LED forward voltage increases and efficiency declines when forward current is increased. Use of constant current with PWM dimming at lower brightness and current dimming at greater brightness (instead of PWM dimming at full brightness range), yields better optical efficiency and resolution especially at lower brightness values. The optimum switch point between PWM and current dimming modes and current slope depend on the LED type.

PWM control ranges from 12.5% to 50% and the current slope can be selected using <GAIN_CTRL[2:0]> and <I_SLOPE[2:0]> EEPROM bits, respectively (see Table 6 and Table 7).

Figure 16. Optical Efficiency Improvement With PWM and Current Dimming

Table 6. Gain Control Selections

GAIN_CTRL[2:0]	SWITCH POINT FROM PWM TO CURRENT DIMMING
000	50.0%
001	40.6%
010	31.3%
011	25.0%
100	21.9%
101	18.8%
110	15.6%
111	12.5%

Table 7. Current Slope Control Selections

I_SLOPE[2:0]	SLOPE GAIN
000	1.000
001	1.023
010	1.047
011	1.070
100	1.094
101	1.117
110	1.141
111	1.164

The current setting for DISP_CL1_CURRENT[11:0] in Hybrid PWM and Current dimming mode can be defined by the following formula (assuming individual LED sink current correction DRV_OUTx_CORR[3:0] is 0%):

Equation 1.

Example of calculation for Hybrid PWM and Current dimming mode, 100-mA maximum output current:

Target maximum current 100 mA	IDISP_CL1_CURRENT = 100 – 100 × 1 × ((100 – 25) / 100) = 25 mA
Maximum scale 100 mA (DRV_LED_CURRENT_SCALE[2:0]=101)
Slope = 1.000 (I_SLOPE[2:0]=000)
Switch point = 25% (GAIN_CTRL[2:0]=011)

Example of calculation for Hybrid PWM and Current dimming mode, 23-mA maximum output current:

Target maximum current 23 mA	IDISP_CL1_CURRENT = 23 – 25 × 1.094 × ((100 – 25) / 100) = 2.49 mA
Maximum scale 25 mA (DRV_LED_CURRENT_SCALE[2:0]=000)
Slope = 1.094 (I_SLOPE[2:0]=100)
Switch point = 25% (GAIN_CTRL[2:0]=011)

NOTE

1. Formula is only approximation for the actual value.
2. DISP_CL1_CURRENT[11:0] value must be chosen to avoid current saturation before 100% brightness is achieved.

8.3.2.7 PWM Calculation Data Flow for Display Mode

Figure 17 shows the PWM calculation data flow for display mode. In PWM direct control mode most of the blocks are bypassed, and this flow chart does not apply.

Figure 17. PWM Data Flow Calculation

Table 8. PWM Calculation Blocks

BLOCK NAME	DESCRIPTION
PWM detector	PWM detector block measures the duty cycle of the input PWM signal. Resolution depends on the input signal frequency. Hysteresis selection sets the minimum allowable change to the input. Smaller changes are ignored.
Brightness register	16-bit register for brightness setting <DISP_CL1_BRT[15:0]>
Brightness mode control	Brightness control block gets 16-bit value from the PWM detector, and also 16-bit value from the brightness register <DISP_CL1_BRT[15:0]>. <BRT_MODE[1:0]> selects whether to use PWM input duty cycle value, the brightness register value or multiplication.
Temperature regulator	Temperature regulator reduces LED PWM duty cycle depending on internal and external temperature sensor. See LED Current Dimming With Internal Temperature Sensor and LED Current Limitation With External NTC Sensor for details
External temperature sensor	External NTC temperature sensor
Internal temperature sensor	Internal die temperature sensor
Sloper	Sloper makes the smooth transition from one brightness value to another. Slope time can be adjusted from 0 ms to 511 ms with <PWM_SLOPE[2:0]> EEPROM bits.
Advanced sloper	Advanced slope makes brightness changes smoother for eye; see Brightness Slope for details
PWM and Current Control	Hybrid PWM and Current dimming improves the optical efficiency of the LEDs by using PWM control with lower brightness values and current control with greater values. <EN_PWM_I> EEPROM bit enables Hybrid PWM and Current control. PWM dimming range can be set 12.5 to 50% of the brightness range with <GAIN_CTRL[2:0]> EEPROM bits. Current slope can be adjusted by using the <I_SLOPE[2:0]> EEPROM bits. See LED Dimming Methods for details
Dither	With dithering the output resolution can be further increased. This way the brightness change steps are not visible to eye. The amount of dithering is 0 to 4 bits, and is selected with <DITHER[2:0]> EEPROM bits.
PWM comparator	PWM comparator compares the PWM counter output to the value received from the dither block. Output of the PWM comparator directly controls the LED current sinks. If Phase Shift PWM (PSPWM) mode is used, the PWM counter values for each LED output are modified by summing an offset value to create different phases.
PWM counter	Overflowing 16-bit PWM counter creates new PWM cycle. Step for incrementation is defined by <PWM_FREQ[3:0]> and <PWM_RESOLUTION[1:0]> bits, see Table 3.

8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme

The PSPWM scheme allows delaying the time when each LED output is active. When the LED outputs are not activated simultaneously, the peak load current from the boost output is greatly decreased. This reduces the ripple seen on the boost output and allows smaller output capacitors. Reduced ripple also reduces the output ceramic capacitor audible ringing. The PSPWM scheme also increases the load frequency seen on boost output up to 4 times, therefore transferring possible audible noise to a frequency above human hearing range. In addition, “optical ripple” through the LCD panel is reduced helping in waterfall noise reduction.

Figure 18 shows the available LED output modes. The number of LED outputs used can be one to four; outputs can be tied together to increase current for one string or all four strings can be independently controlled in the cluster mode.

In <LED_STRING_CONF[2:0]> = 000 the phase difference between channels is 90 degrees. This mode is intended for application in Figure 53. When <LED_STRING_CONF[2:0] > = 001 the phase difference between 3 channels in display mode is 120 degrees. This mode is intended for application shown in Figure 63. When <LED_STRING_CONF[2:0]> = 010 the phase difference between 2 channels in display mode is 180 degrees, channels 3 and 4 in cluster mode, intended for application illustrated by Figure 60. LED strings not used in Display mode can be used for Cluster mode, or not used. When <LED_STRING_CONF[2:0]> = 111 all strings are in cluster mode.

Figure 18. Phase Shift Modes

8.3.4 LED Current Setting

Figure 19. LED Current Setting

The output LED current can be set by a register. Maximum output LED current can be set by an external resistor when that option is enabled. For strings in cluster mode current for every LED output can be set independently.

The maximum current for the LED outputs in display mode are controlled with <DISP_CL1_CURRENT [11:0]> bits. Current for the outputs in the cluster mode are controlled separately by the register bits <DISP_CL1_CURRENT[11:0]>, <CL2_CURRENT[7:0]>, <CL3_CURRENT[7:0]>, and <CL4_CURRENT[7:0]> respectively. In the display mode resolution for current control is 12 bits. In the cluster mode resolution is 8 bits for all outputs except OUT1. For OUT1 maximum current resolution is always 12 bits.

Additionally, current for every output current can be scaled with <DRV_LED_CURRENT_SCALE[2:0]> bits (see Table 11) and can be corrected by <DRV_OUTx_CORR[3:0]> EEPROM bits. The adjustment range is shown in Table 12 Maximum current settings are effective for display and cluster modes.

When maximum current is controlled by anexternal resistor R_ISET (<DRV_EN_EXT_LED_CUR_CTRL>=1), current for outputs in display mode or for OUT1 in cluster mode can be calculated as follows:

Equation 2.

Where V_BG = 1.2 V.

space

For example, if <DISP_CL1_CURRENT[11:0]> is 0xFFF, <DRV_LED_CURRENT_SCALE[0:2]> is 111, and a 24-kΩ R_ISET resistor is used, then the LED maximum current is 150 mA.

When current control with external resistor is disabled (<DRV_EN_EXT_LED_CUR_CTRL>=0) LED current for outputs in display mode or for OUT1 in cluster mode can be calculated as follow:

Equation 3.

When maximum current control with external resistor is enabled, LED current for OUT2…OUT4 outputs in cluster mode is defined as:  

Equation 4.

Otherwise, when current control with external resistor is disabled:

Equation 5.

Correction value is defined by <DRV_OUTx_CORR[3:0]> shown in Table 12:

The <DISP_CL1_CURRENT[11:0]> register is initialized during start-up by the <LED_CURRENT_CTRL[11:0]> EEPROM bits. <DRV_LED_CURRENT_SCALE[2:0]> are initialized by the <DRV_LED_CURRENT_SCALE[2:0]> EEPROM bits. Cluster mode current registers for outputs OUT2 and OUT3 are initialized by 0 during power on reset.

Current register value must be not written to 0 if brightness is not zero – it may cause LED faults and adaptive voltage control instability.

8.3.5 Cluster Mode

Cluster is a simplified mode which allows independent current and PWM control for every string in cluster mode. In this mode brightness control is limited to conventional PWM through the SPI/I²C brightness registers. The PWM input pin, Hybrid PWM and Current dimming mode, slope control, or dither are not available. Brightness for different LED strings depends on <DISP_CL1_BRT[15:0]>, <CL2_BRT[12:0]>, <CL3_BRT[12:0]> and <CL4_BRT[12:0]> registers. If OUT1 is in cluster mode, only 13 MSB are used. If all LED outputs are in the cluster mode, LED output PWM resolution is always 13 bits, and frequency depends on <PWM_RESOLUTION[1:0]> bits (see Table 13). If one or more of the LED outputs is in display mode, frequency, and resolution for strings in the cluster mode is the same as for strings in the display mode (see Table 1).

Figure 20. Cluster Mode Block Diagram

When the LP8860-Q1 is set in cluster mode, fault protection functionality is limited. Headroom for LED strings must be between the high-voltage comparator level <DRV_LED_FAULT_THR[1:0]> and low-voltage comparator level <DRV_HEADR[2:0]> (which depend upon saturation voltage); otherwise a fault is generated.

Adaptive boost control does not follow strings in cluster mode. Display mode strings and cluster mode strings must not be connected to the same boost. When LED strings in display and cluster modes are connected to the same boost, LED open or short faults may be generated if the LED forward-voltage mismatch is too high.

If all LED outputs are in cluster mode, boost output voltage is fixed and must be set by EEPROM <BOOST_INITIAL_VOLTAGE[5:0]> bits to a value high enough to ensure correct LED string operation in all conditions.

<EN_CL_LED_FAULT>=0 disables cluster LED fault detection, even if all LED strings are in the cluster mode. The current de-rating (based on the internal temperature sensor) and LED current limitation (based on external temperature sensor) are not functional in this mode, and analog current dimming based on the external sensor functionality is limited (LED shutdown for high temperature is not operational).

8.3.6 Boost Controller

The LP8860-Q1 boost controller generates a 16-V to 48-V supply voltage for the LEDs. Output voltage can be increased by an external resistive voltage divider connected to the FB pin, but voltage lower than 16 V is not supported.

The output voltage can be controlled either with EEPROM register bits <BOOST_INITIAL_VOLTAGE[5:0]>, or automatic adaptive boost control can be used. During start-up the output voltage is ramped to default start-up voltage <BOOST_INITIAL_VOLTAGE[5:0]> where it then adapts to the required voltage based on LED output headroom voltage (if adaptive mode has been enabled in EEPROM). Initial voltage for adaptive voltage control mode must be higher than LED string voltage — otherwise the system may generate a boost overvoltage fault during VDDIO/EN pin toggling if the output boost capacitor is not discharged below the initial voltage before the next boost start-up. A different option is to set <MASK_BOOST_OVP_STATUS> bit high to prevent a boost overvoltage fault.

The converter is a magnetic switching PWM mode DC-DC converter with a current limit. The topology of the magnetic boost converter is called Current Programmed Mode (CPM) control, where the inductor current is measured and controlled with the feedback. Switching frequency is selectable from 100 kHz and 2.2 MHz with EEPROM bits <BOOST_FREQ_SEL[2:0]>. In most cases lower frequency has the highest system efficiency.

In adaptive mode the boost output voltage is adjusted automatically based on LED current sink headroom voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible current sink headroom and high efficiency. The adaptive mode is enabled with the <EN_ADAP EEPROM> bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <BOOST_INITIAL_VOLTAGE[5:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started after VDDIO/EN toggling or power-on reset.

Boost can be clocked by an external SYNC signal (100 kHz to 2.2 MHz); minimum pulse length for the signal is 200 ns. If an external SYNC disappears, boost uses internal frequency defined by <BOOST_FREQ_SEL[2:0]> EEPROM bits. The boost frequency with external SYNC and EEPROM bits-defined frequency need to be close to each other; maximum frequency mismatch is ±25%. The boost controller has optional spread-spectrum switching operation (±3% from central frequency, 1.875-kHz modulation frequency) which reduces spectrum spikes around the switching frequency and its harmonic frequencies.

Further EMI reduction can be achieved by limiting the rise and fall times of the FET with an additional external resistor on the GD pin.

The boost gate driver is powered directly from VDD voltage or from the charge pump which multiplies V_DD voltage by 2. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.

Figure 21. Boost Converter Topology

8.3.7 Charge Pump

The boost switch FET gate driver is powered typically from VDD voltage. When the VDD voltage is not high enough to drive the boost FET gate, the charge pump can be used to increase gate-driver voltage.

The charge pump effectively doubles the VDD voltage for gate driver. Maximum DC output current is 50 mA. Boost driver voltage selection bit BOOST_GD_VOLT must be set to 1 before enabling the charge pump. If VDD voltage is 5 V, the charge pump is not typically needed. In this case, a flying capacitor is not necessary, and the charge pump output CPUMP pin must be connected to the VDD input pin.

Figure 22. Charge Pump

Square-waveform (SQW) output provides a 100-kHz square wave signal (1 mA max) with amplitude equal to the charge pump output voltage. When the charge pump is disabled, amplitude of this voltage is equal to VDD. This signal can be used to generate low-current voltage rails; for example, a gate-reference voltage for output protective FET (Figure 61) or for using nMOSFET as power-line FET (Figure 25). Figure 23 and Figure 24 show examples of possible connections.

Figure 23. V_RAIL Multiplied by 2

Figure 24. V_RAIL Multiplied by 4

Figure 25. Using nFET for Power-Line Control

8.3.8 Powerline Control FET

The power-line FET limits peak current from the power line during start-up and allows the boost and LED strings to be disconnected during a fault condition, when device is in fault recovery state.

The power-line control block has VSENSE_P and VSENSE_N pins for sensing input current and a shutdown SD pin for driving the gate of the power-line FET. The power-line FET is opened when the LP8860-Q1 is enabled by VDDIO/EN signal and V_IN is greater than V_GS in steady state (when pFET is used as a power-line FET). A power-line pFET must be chosen with minimal V_GS in steady state. Gate current is defined by the <PL_SD_SINK_LEVEL[1:0]> EEPROM bits.

Figure 26. Power-line FET Control

During a shutdown state the LP8860-Q1 closes the power-line FET and prevents possible boost and LED leakage. Sense pins are used to detect overcurrent. Power-line FET is closed when an OCP fault occurs. A VIN OCP is indicated with PL_FET_FAULT bit. The power-line FET closes with all faults, followed by entering to a recovery state.

When it is not possible to choose a pFET with the necessary characteristics, a schematic with nFET can be used (see Charge Pump section, Figure 25); the <NMOS_PLFET_EN EEPROM> bit must be set accordingly. In this case the SD pin provides current to shut down the power-line nFET during fault condition.

8.3.9 Protection and Fault Detection Modes

The LP8860-Q1 has fault detection for LED outputs, low and high input voltage, power line overcurrent, boost overcurrent, boost overvoltage, and charge pump overload. In addition, the device has thermal shutdown and LED overtemperature protection with an external NTC thermistor.

Faults have dedicated fault flags in registers <FAULT> and <LED_FAULT>. Mask bits can be used to disable certain faults (see Table 17 for details). In addition the open-drain output pin FAULT can be used to indicate occurred fault. Writing CLEAR_FAULTS or setting the NSS pin (I²C interface mode only) high resets the fault. Setting the VDDIO/EN pin low, then high again, resets the faults as well.

8.3.9.1 LED Fault Comparators and Adaptive Boost Control

Every LED current sink has 3 comparators for adaptive boost control and fault detection. Each comparator outputs is filtered. Filter control bits <BL_COMP_FILTER_SEL [3:0]> select how many PWM generator clock cycles (5 MHz if PLL disabled or PLL clock) high/mid comparator is filtered before it is used to detect shorted LEDs and boost voltage down-scaling. Usually 1 µs is sufficient; for 5-MHz frequency it means <BL_COMP_FILTER_SEL [3:0]> = 0000b, 10 MHz = 0001b, 20 MHz = 0010b, and 40 MHz = 0011b.

Adaptive boost-control function adjusts the boost output voltage to the minimum sufficient voltage for proper LED current sink operation. The output with the highest V_F LED string is detected and the boost output voltage adjusted accordingly. Current sink headroom can be adjusted with EEPROM bits <DRV_HEADR[2:0]>. Boost adaptive control voltage step size is 125 mV. Boost adaptive control operates similarly with and without PSPWM. Additionally, when faster boost response is needed in larger brightness steps, the "jump" command can be used. Jump allows increase of the boost voltage with greater steps. Jump is enabled with the <EN_JUMP> EEPROM bit. The threshold for the magnitude of brightness increase that requires use of jump can be set with the <JUMP_STEP_SIZE[1:0]> EEPROM bits. <BRIGHTNESS_JUMP_THRES[1:0]> EEPROM bits define when the jump command is activated.

Figure 27. Boost Voltage Adaptation

Figure 28. Output Voltage Comparators

Figure 29 shows different cases which cause boost voltage increase, decrease, or generate faults.

Figure 29. Protection and Boost Adaptation Algorithms

NOTE

In the Cluster mode, if voltage of one or more outputs is below LOW_COMP, it causes open LED fault detection.

8.3.9.2 LED Current Dimming With Internal Temperature Sensor

The LP8860-Q1 can prevent thermal shutdown (TSD) by reducing the average LED strings current based on die temperature.

When die temperature reaches <INT_TEMP_LIM[1:0]> EEPROM bits-defined threshold, the device automatically lowers the brightness (2.25% / ºC typical). Depending on brightness control mode either PWM duty cycle or current is used for average current reduction.

Figure 30. Thermal De-Rating Function
Example With 100% and 50% Brightness

Table 15. Thermal De-rating Function Temperature Thresholds

INT_TEMP_LIM[1:0]	TEMPERATURE
00	disabled
01	90ºC
10	100ºC
11	110ºC

Table 16. Temperature ADC Output for Different Temperatures

TEMPERATURE (°C)	DECIMAL OUTPUT VALUE OF TEMP[10:0] REGISTER
	VDD 3.6 (V)	VDD 5 (V)
–40	885	891
–35	901	907
–30	916	923
–25	932	939
–20	948	954
–15	964	970
-10	980	986
-5	994	1002
0	1010	1018
5	1026	1034
10	1041	1050
15	1057	1066
20	1073	1082
25	1089	1098
30	1105	1115
35	1121	1131
40	1137	1147
45	1154	1163
50	1170	1180
55	1186	1196
60	1202	1212
65	1219	1229
70	1235	1245
75	1252	1262
80	1268	1278
85	1285	1293
90	1301	1310
95	1318	1328
100	1332	1343
105	1349	1359
110	1365	1375

8.3.9.3 LED Current Limitation With External NTC Sensor

The <EXT_TEMP_COMP_EN> EEPROM bit enables the LED current limitation mode. The principle of current limitation is shown in Figure 31.

When LED temperature reaches <EXT_TEMP_LEVEL_LOW[3:0]> level, the device automatically tries to reduce LED average current step-by-step by 3.125% from maximum brightness value. Step time is defined by <EXT_TEMP_PERIOD[4:0]> EEPROM bits. If temperature continues to increase and reaches <EXT_TEMP_LEVEL_HIGH[3:0]> level, the device shuts down the LEDs and generates a fault condition. The LEDs are turned on automatically when the temperature is below the <EXT_TEMP_LEVEL_LOW[3:0]> level. Otherwise, if after one or more steps the temperature drops down below <EXT_TEMP_LEVEL_LOW[3:0]>, brightness increases with the same step time until it reaches the original level. The LP8860-Q1 uses PWM duty reduction to reduce LED current. The device detects external NTC resistor availability, and the <TEMP_RES_MISSING> flag is set, if the NTC sensor is missing (resistance is 2 MΩ or more).

Figure 31. LED Current Limitation With NTC

Figure 32. Timing Diagram for LED Current Limitation With NTC

8.3.9.4 LED Current Dimming With External NTC Sensor

When an external resistor for maximum current control is used, current dimming for LED current can be used also. In this case LED current can be de-rated when ambient temperature is high. This option must be enabled by <EXT_TEMP_I_DIMMING_EN> and <EXT_TEMP_COMP_EN> EEPROM bits.

Knee point and slope are defined by <EXT_TEMP_MINUS[1:0]> and <EXT_TEMP_GAIN[3:0]> EEPROM bits respectively. LED shutdown temperature is defined by <EXT_TEMP_LEVEL_HIGH[3:0]> bits. Serial and parallel resistors R1 and R2 affect the slope and knee point and can be used for the thermal curve adjustment and NTC linearization.

Figure 33. Current Dimming for High Ambient Temperature

Figure 34. NTC Linearization

Figure 35 and Figure 36 show the block diagrams for current dimming.

Figure 35. Temperature-Dependent NTC Current
(Subtracted from ISET Current)

Figure 36. NTC Current Processing —
Scaling, Shift, and Limitation

Current dimming by external NTC sensor for 150-mA scale can be defined by formulas:

Equation 6.

Equation 7.

I_TEMP cannot be negative; if I_TEMP < 0, then I_TEMP must be 0.

Equation 8. I_LED = (I_SET – I_TEMP) × 150 mA

where

• I_SET:   Maximum current setting with external resistor R_ISET, µA
• I_TEMP:  Temperature compensation, µA
• R_ISET: External resistor, kΩ
• R1, R2:   Resistors for adjustment, kΩ
• I_LED: Output current per channel, mA
• EXT_TEMP_MINUS[1:0]:  1, 5, 9, 13 µA
• EXT_TEMP_GAIN[[3:0]:  50/n, n = 16 to 1
• V_BG: 1.2 V

8.3.9.5 Protection Feature and Fault Summary

Table 17 summarizes protection features and related faults.

Table 17. Overview of the Fault/Protection Schemes

FAULT/PROTECTION	FAULT NAME	THRESHOLD		ACTION(1)(2)	MASK(4)	FAULT CLEARING(3)(5)
Input overvoltage protection	VIN_OVP	OVP_LEVEL[1:0] (V)		VIN overvoltage monitored from soft start. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared. FAULT pin is pulled low.	MASK_OVP_FSM Masks fault recovery, but not status and fault pin operations	Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
		00	OFF
		01	7
		10	11
		11	22.5
Input undervoltage protection	VIN_UVLO	UVLO_LEVEL[1:0] (V)		VIN undervoltage monitored from soft start. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared. FAULT pin is pulled low.	MASK_VIN_UVLO Masks fault recovery, status and fault pin operations	Fault bit and FAULT pin: 1.POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
		00	OFF
		01	3
		10	5
		11	8
VDD undervoltage protection	VDD_UVLO	VDD_UVLO_LEVEL Threshold (V)		Device enters STANDBY state. Recovers when fault disappears. All registers are cleared or reloaded from EEPROM (if defined) with exception registers 0x00, 0x01, 0x04…0x0C. After recovery LP8860-Q1 provides the same brightness as before fault detection, if DISP_CL1_CURRENT[11:0] context stays same as LED_CURRENT_CTRL[11:0] EEPROM setting. If VDD voltage goes below POR level, registers 0x00, 0x01, 0x04…0x0C are cleared. This fault does not have any flags and doesn’t generate FAULT. Voltage hysteresis is 50 mV (typical).
		0	2.5
		1	3
Boost overcurrent protection	BOOST_OCP	VBOOST longer than 110 ms 5 V (typical) below set value. Set value is voltage value defined by logic during adaptation in adaptive mode or initial boost voltage setting in manual mode.		Fault monitoring started from boost start. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared. FAULT pin is pulled low.	MASK_BOOST_OCP_ FSM Masks fault recovery, but not status and fault pin operations	Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
Boost overvoltage protection	BOOST_OVP	VBOOST voltage 1.6 V (typical) above set value Set value is voltage value defined by logic during adaptation in adaptive mode or initial boost voltage setting in manual mode.		Boost OVP fault monitored during normal operation FAULT pin is pulled low.	MASK_BOOST_OVP_ STATUS	Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
Input voltage overcurrent protection	PL_FET_FAULT	PL_SD_LEVEL[1:0] (A)		Fault is detected with 2 methods: 1. Detects overcurrent from soft start by measuring RISENSE voltage. 2. Detects FB voltage at the end of soft start. If voltage is below 1.2 V, fault is detected. Fault causes entry to FAULT_RECOVERY state. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared. FAULT pin is pulled low.		Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
		10	6
		11	8
Short LED fault	SHORT_LED	DRV_LED_FAULT_THR[1:0] (V)		LED output in display mode: Triggered if one or more outputs voltage is above DRV_LED_FAULT_THR and at least one LED output voltage is between DRV_HEADR and DRV_HEADR + DRV_LED_COMP_HYST. Is set only if LED faults are enabled in EEPROM. Shorted string is removed from voltage control loop and LED current sink n is disabled. LED output in cluster mode: If one or more outputs voltage above DRV_LED_FAULT_THR fault is detected. Is pulled low only if LED faults are enabled in EEPROM. Shorted string PWM output is disabled. FAULT pin is pulled low.	EN_DISPLAY_LED_ FAULT for LEDs in display mode EN_CL_LED_FAULT for LEDs in cluster mode	Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin When fault is cleared it can be set again only during next POR or if there is another LED short fault in different output.
		00	3.6
		01	3.6
		10	6.9
		11	10.6
		DRV_LED_COMP_HYST[1:0] (mV)
		00	1000
		01	750
		10	500
		11	250
Open LED fault	OPEN_LED	DRV_HEADR[2:0] (mV)		LED output in display mode: Triggered if one or more outputs voltage is below DRV_HEADR, and boost adaptive control has reach the maximum voltage. Is set only if led faults enabled in EEPROM. Open string is removed from voltage control loop and PWM generation is disabled. LED output in cluster mode: Triggered if one or more outputs voltage is below DRV_HEADR. Is set only if LED faults enabled in EEPROM. Open string PWM generation is disabled. FAULT pin is pulled low.	EN_DISPLAY_LED _FAULT for LEDs in display mode EN_CL_LED_FAULT for LEDs in cluster mode	Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin When open fault is cleared it can set again only during next power-up or if there is another LED open fault.
		111	VSAT+50
		110	VSAT+175
		101	VSAT+300
		100	VSAT+450
		011	VSAT+575
		010	VSAT+700
		001	VSAT+875
		000	VSAT+1000
LED faults	LED_FAULT[4:1]			Defines which string has either open or short fault. Cleared only during power down.		POR or VDDIO/EN
Charge pump fault	CP_2X_ FAULT	VCPUMD < 0.85 × (2 × VDD) (typical)		Charge pump voltage not high enough condition. Fault causes entry to FAULT_RECOVERY state. CP voltage monitored from the boost soft start. If device is restarted successfully with recovery timer, the fault register bit is not automatically cleared. FAULT pin is pulled low.		Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
Thermal Current Limit (LED Outputs)	No faults	INT_TEMP_LIM[1:0]		When die temperature increases temperature defined by INT_TEMP_LIM[1:0] the device automatically lowers the PWM duty for outputs 2.25%/ºC (typical). For Hybrid PWM and Current dimming mode current is used for brightness reduction as well.
		00 01 10 11	disabled 90°C 100°C 110°C
Thermal LED Current Limit with external NTC sensor.	EXT_TEMP_ FLAG_L	EXT_TEMP_LEVEL_LOW[3:0]		Fault is monitored during normal operation. If EXT_TEMP_LEVEL_LOW[3:0] is exceeded, LED current is reduced. FAULT pin is pulled low when EXT_TEMP_FLAG_L goes high.	EXT_TEMP_COMP_EN=0 disables fault	Fault bit: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin when fault deasserted. Fault pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
		Setting	Level (kΩ)
		0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111	79.67 43.35 29.77 22.67 18.30 15.34 13.21 11.60 10.34 9.32 8.49 7.79 7.20 6.69 6.25 5.87
	EXT_TEMP_ FLAG_H	EXT_TEMP_LEVEL_HIGH[3:0]		Fault is monitored during normal operation. If EXT_TEMP_LEVEL_HIGH[3:0] limit is exceeded, the LED outputs are turned off. FAULT pin is pulled low.	EXT_TEMP_COMP_EN=0 disables fault	Fault bit: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin when fault deasserted. Fault pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
		Setting	Level (kΩ)
		0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111	79.67 43.35 29.77 22.67 18.30 15.34 13.21 11.60 10.34 9.32 8.49 7.79 7.20 6.69 6.25 5.87
NTC missing	TEMP_RES_ MISSING	Resistance > 2 MΩ		NTC is missing. Fault is monitored during normal operation. Not connected to FAULT output pin. TEMP_RES_FAULT is monitored if EXT_TEMP_COMP_EN EEPROM bit has been enabled	EXT_TEMP_COMP_EN=0 disables fault	1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin
Thermal shutdown	TSD	Rising temperature =165ºC Falling temperature = 135ºC		Thermal shutdown is monitored from soft start. Fault causes entry to the FAULT_RECOVERY state. FAULT pin is pulled low.		Fault bit and FAULT pin: 1. POR or VDDIO/EN 2. Writing CLEAR_FAULTS bit or toggling NSS pin

(1) Recovery time is 100 ms.

(2) During fault recovery state the LED outputs and boost is shut down and power-line FET is turned off.

(3) If fault is cleared during fault recovery state, FAULT pin is pulled low again after recovery state, if this fault still exists.

(4) If fault recovery is masked, fault bit sets again after cleaning.

(5) The NSS pin can be used for fault reset only for I²C interface mode. NSS is level sensitive; be aware NSS is set to low after fault reset.

Fault detection is digitally filtered — filtering time for different faults is shown in Table 18.

Table 18. Fault Filters

FAULT/PROTECTON	FAULT NAME	TIME	ENABLED
Boost Overcurrent Protection	BOOST_OCP	110 ms	From boost start
Boost Overvoltage Protection	BOOST_OVP	100 µs	In normal mode
Input Overvoltage Protection	VIN_OVP	100 µs	From soft start
Input Undervoltage Protection	VIN_UVLO	100 µs	From soft start
Input Overcurrent Protection	PL_FET_FAULT	100 µs	From soft start
VDD Undervoltage Protection	VDD_UVLO	5 µs	Always
Thermal Shutdown	TSD	100 µs	From soft start
Charge Pump fault	CP_2X_FAULT	10 µs	From boost start
Thermal LED Current Limit with external NTC sensor.	EXT_TEMP_FLAG_H	10 µs	In normal mode
	EXT_TEMP_FLAG_L	10 µs	In normal mode
NTC missing	TEMP_RES_FAULT	100 µs	In normal mode

Figure 37. Input OVP Triggering and Recovery

Figure 39. Input OVP Triggering and Recovery

Figure 41. Boost OVP Triggering and Recovery

Figure 38. Input UVLO Triggering and Recovery

Figure 40. Boost OCP Triggering and Recovery

8.4.1 Standby Mode

The device is in standby mode when the EN/VDDIO pin is low. Current consumption from the VDD pin in this mode is typically 1 µA.

8.4.2 Active Mode

The EN/VDDIO pin enables the logic and analog blocks. The device goes through the start-up sequence where EEPROM context is loaded to the registers, the power-line FET is enabled during soft start, and boost starts during boost start-time. In this mode I²C and SPI communication are available after soft start, and register settings can be changed.

8.4.3 Fault Recovery State

Fault recovery state is special state which can be caused by faults. In this state power line FET is switched off, boost and LED current sinks are disabled. I²C or SPI interfaces are available in this state — for example, fault flags can be read.

8.4.4 Start-Up and Shutdown Sequences

Depending on EEPROM settings the LP8860-Q1 can be started up or shut down differently. Typical start-up/shutdown sequence is shown in Figure 43.

Figure 43. Timing Diagram for the Typical Start-Up and Shutdown

8.5.1 EEPROM

EEPROM memory stores various parameters for chip control. The 200-bit EEPROM memory is organized as 25 × 8 bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register data can be read and written through the I²C/SPI serial interface. EEPROM must be burned with the new data; otherwise, data disappears after power-on reset or VDDIO/EN cycling. PWM outputs and PLL must be disabled when writing to EEPROM registers or burning EEPROM (<DISP_CL1_BRT[15:0]> = 0, <CL2_BRT[12:0]> = 0, <CL3_BRT[12:0]> = 0, <CL2_BRT[12:0]> = 0, <EN_PLL> = 0). To read and program EEPROM NVM separate commands need to be sent. Erase and program voltages are generated internally; no other voltages other than the normal VDD voltage is required. A complete EEPROM memory map is shown in the Table 23.

The user must make sure that VDD power is on, and the VDDIO/EN pin is kept high, during the whole programming/burn sequence to avoid memory corruption.

Figure 44. EEPROM and Register Configuration

EEPROM has protection against accidental writes. EEPROM access can be unlocked by writing a pass code to the EEPROM_UNLOCK register. It unlocks the EEPROM Control register EEPROM_CNTRL and all EEPROM registers. Lock is enabled again by writing any other code to the EEPROM_UNLOCK register (for example, 0x00 enables the lock any time).

EEPROM is used as fixed product-configuration storage, to be set or programmed during production before normal operation. EEPROM can be reprogrammed for evaluation purposes up to 1000 cycles. Data-retention lifetime for factory-programmed content is 10 years, minimum. For more details regarding EEPROM options, see TI Application Note Selecting the Correct LP8860-Q1 EEPROM Version (SNVA757).

8.5.2 Serial Interface

The LP8860-Q1 supports 2 different interface modes:

• SPI interface (4-wire serial)
• I²C-compatible (2-wire serial)

The user can define the interface mode by IF pin as shown in Table 20. The LP8860-Q1 detects interface mode selection during start-up. When the device is in normal mode, the IF signal does not affect the interface selection.

8.5.2.1 SPI Interface

The LP8860-Q1 is compatible with SPI serial-bus specification, and it operates as a slave. The transmission consists of 16-bit write and read cycles. One cycle consists of 7 address bits, 1 read/write (R/W) bit, and 8 data bits. The R/W bit high state defines a write cycle and low defines a read cycle. MISO output is normally in a high-impedance state. When the slave select NSS for LP8680 is active (that is, low), MISO output is pulled low for both read and write operations, except for the period when Data is sent out during a read cycle. The Address and Data are transmitted MSB first. The Slave Select signal NSS must be low during the Cycle transmission. NSS resets the interface when high, and it has to be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK.

Figure 45. SPI Write Cycle

Figure 46. SPI Read Cycle

8.5.2.2 I²C Serial Bus Interface

8.5.2.2.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol is using a two-wire interface for bi-directional communications between the devices connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines must be connected to a positive supply through a pullup resistor and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the SCL. The LP8860-Q1 is always a slave device.

8.5.2.2.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL. Consequently, throughout the clock high period, the data must remain stable. Any changes on the SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data must be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock.

Figure 47. Bit Transfer

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process.

Figure 48. Start and Stop

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.

Figure 49. Stop and Start Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed, or a register read cycle.

8.5.2.2.3 Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte.

8.5.2.2.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging (negative acknowledge”) the last byte clocked out of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down.

8.5.2.2.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LP8860-Q1 operates as a slave device with 7-bit address combined with data direction bit. Default slave address is 2Dh as 7-bit or 5Ah for write and 5Bh for read in 8-bit format.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device sends an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.

Figure 50. Address and Read/Write Bit

8.5.2.2.6 Control Register Write Cycle

1. Master device generates start condition.
2. Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).
3. Slave device sends acknowledge signal if the slave address is correct.
4. Master sends control register address (8 bits).
5. Slave sends acknowledge signal.
6. Master sends data byte to be written to the address register.
7. Slave sends acknowledgement.
8. Write cycle ends when the master creates stop condition.

8.5.2.2.7 Control Register Read Cycle

1. Master device generates start condition.
2. Master device sends slave address (7 bits) and the data direction bit (r/w = “0”).
3. Slave device sends acknowledge signal if the slave address is correct.
4. Master sends control register address (8 bits).
5. Slave sends acknowledge signal if slave address is correct.
6. Master generates repeated start condition
7. Master sends the slave address (7 bits) and the data direction bit (r/w = “1”)
8. Slave sends acknowledgment if the slave address is correct.
9. Read cycle ends when master does not generate acknowledge signal after data byte and generates stop condition.

Table 21. Data Read and Write Cycles

MODE	ACTION(1)
Data Read	<Start Condition>
	<Slave Address><r/w = ‘0’>[Ack]
	<Register Addr.>[Ack]
	<Repeated Start Condition>
	<Slave Address><r/w = ‘1’>[Ack]
	[Register Data]<Ack or Nack>
	register address possible
	<Stop Condition>
Data Write	<Start Condition>
	<Slave Address><r/w=’0’>[Ack]
	<Register Addr.>[Ack]
	<Register Data>[Ack]
	register address possible
	<Stop Condition>

(1) <> Data from master; [] Data from slave

Figure 51. Register Write Format

Figure 52. Register Read Format

Table 22. Register Map

Table 23. EEPROM Register Map⁽¹⁾

8.6.1 Register Bit Explanations

8.6.2 EEPROM Bit Explanations