11.1 Layout Guidelines

Figure 67 shows a layout recommendation for the LP8860-Q1. Figure 67 is used to show the principles of good layout. This layout can be adapted to the actual application layout if and where possible. It is important that all boost components are close to each other and to the device; the high-current traces must be wide enough. VDD must be as noise-free as possible. Place a VDD bypass capacitor near the pin and ground it to a noise-free ground. A charge-pump capacitor and boost input and output capacitors must be connected to PGND. Here are some main points to help the PCB layout work:

• Current loops need to be minimized:
  • For low frequency the minimal current loop can be achieved by placing the boost components as close to each other as possible. Input and output capacitor grounds need to be close to each other to minimize current loop size.
  • Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High frequency return currents try to find route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route.
  • For high frequency the copper area capacitance must be taken into account. For example, the copper area for the drain of boost nMOSFET is a tradeoff between capacitance and components cooling capacity.
• GND plane must be intact under the high current boost traces to provide shortest possible return path and smallest possible current loops for high frequencies.
• Current loops when the boost switch is conducting and not conducting must be in the same direction in optimal case.
• Inductors must be placed so that the current flows in the same direction as in the current loops. Rotating the inductor 180° changes current direction.
• Use separate power and noise-free grounds. The power ground is used for boost converter return current and noise-free ground for more sensitive signals, like VDD bypass capacitor grounding as well as grounding the GND pins of the LP8860-Q1 itself.
• Boost output feedback voltage to LEDs need to be taken out after the output capacitors, not straight from the diode cathode.
• A small (for example, 39-pF) bypass capacitor must be placed close to the FB pin to suppress high frequency noise
• VDD line must be separated from the high current supply path to the boost converter to prevent high frequency ripple affecting the chip behavior. A separate 1-µF bypass capacitor is used for the VDD pin, and it is grounded to noise-free ground.
• Capacitor connected to charge pump output CPUMP must have 10-µF capacitance, grounded by shortest way to boost switch current sensing resistor. This capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.
• Input and output capacitors need strong grounding (wide traces, many vias to PGND plane).
• If two or more output capacitors are used, symmetrical layout must be used to get all capacitors working ideally.
• Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to become unstable on some loads. DC bias characteristics need to be obtained from the component manufacturer; it is not taken into account on component tolerance. TI recommends X5R/X7R capacitors.

11.2 Layout Example

Figure 67. LP8860-Q1 Layout