SNVSA21G May   2014  – October 2017 LP8860-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Current Sinks Electrical Characteristics
    7. 7.7  Boost Converter Characteristics
    8. 7.8  Logic Interface Characteristics
    9. 7.9  VIN Undervoltage Protection (VIN_UVLO)
    10. 7.10 VDD Undervoltage Protection (VDD_UVLO)
    11. 7.11 VIN Overvoltage Protection (VIN_OVP)
    12. 7.12 VIN Overcurrent Protection (VIN_OCP)
    13. 7.13 Power-Line FET Control Electrical Characteristics
    14. 7.14 External Temp Sensor Control Electrical Characteristics
    15. 7.15 I2C Serial Bus Timing Parameters (SDA, SCLK)
    16. 7.16 SPI Timing Requirements
    17. 7.17 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Boost Controller
      2. 8.1.2 LED Output Configurations
      3. 8.1.3 Display Mode
      4. 8.1.4 Cluster Mode
      5. 8.1.5 Hybrid Dimming
      6. 8.1.6 Charge Pump and Square Waveform (SQW) Output
      7. 8.1.7 Power-Line FET
      8. 8.1.8 Protection Features
      9. 8.1.9 Advanced Thermal Protection Features
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Generation
        1. 8.3.1.1 LED PWM Clock Generation With VSYNC
        2. 8.3.1.2 LED PWM Frequency and Resolution
      2. 8.3.2 Brightness Control (Display Mode)
        1. 8.3.2.1 PWM Input Duty Cycle Based Control
        2. 8.3.2.2 Brightness Register Control
        3. 8.3.2.3 PWM Input Duty × Brightness Register
        4. 8.3.2.4 PWM-Input Direct Control
        5. 8.3.2.5 Brightness Slope
        6. 8.3.2.6 LED Dimming Methods
        7. 8.3.2.7 PWM Calculation Data Flow for Display Mode
      3. 8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme
      4. 8.3.4 LED Current Setting
      5. 8.3.5 Cluster Mode
      6. 8.3.6 Boost Controller
      7. 8.3.7 Charge Pump
      8. 8.3.8 Powerline Control FET
      9. 8.3.9 Protection and Fault Detection Modes
        1. 8.3.9.1 LED Fault Comparators and Adaptive Boost Control
        2. 8.3.9.2 LED Current Dimming With Internal Temperature Sensor
        3. 8.3.9.3 LED Current Limitation With External NTC Sensor
        4. 8.3.9.4 LED Current Dimming With External NTC Sensor
        5. 8.3.9.5 Protection Feature and Fault Summary
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Fault Recovery State
      4. 8.4.4 Start-Up and Shutdown Sequences
    5. 8.5 Programming
      1. 8.5.1 EEPROM
      2. 8.5.2 Serial Interface
        1. 8.5.2.1 SPI Interface
        2. 8.5.2.2 I2C Serial Bus Interface
          1. 8.5.2.2.1 Interface Bus Overview
          2. 8.5.2.2.2 Data Transactions
          3. 8.5.2.2.3 Acknowledge Cycle
          4. 8.5.2.2.4 Acknowledge After Every Byte Rule
          5. 8.5.2.2.5 Addressing Transfer Formats
          6. 8.5.2.2.6 Control Register Write Cycle
          7. 8.5.2.2.7 Control Register Read Cycle
    6. 8.6 Register Maps
      1. 8.6.1 Register Bit Explanations
        1. 8.6.1.1  Display/Cluster1 Brightness Control MSB
        2. 8.6.1.2  Display/Cluster1 Brightness Control LSB
        3. 8.6.1.3  Display/Cluster1 Output Current MSB
        4. 8.6.1.4  Display/Cluster1 Output Current LSB
        5. 8.6.1.5  Cluster2 Brightness Control MSB
        6. 8.6.1.6  Cluster2 Brightness Control LSB
        7. 8.6.1.7  Cluster2 Output Current
        8. 8.6.1.8  Cluster3 Brightness Control MSB
        9. 8.6.1.9  Cluster3 Brightness Control LSB
        10. 8.6.1.10 Cluster3 Output Current
        11. 8.6.1.11 Cluster4 Brightness Control MSB
        12. 8.6.1.12 Cluster4 Brightness Control LSB
        13. 8.6.1.13 Cluster4 Output Current
        14. 8.6.1.14 Configuration
        15. 8.6.1.15 Status
        16. 8.6.1.16 Fault
        17. 8.6.1.17 LED Fault
        18. 8.6.1.18 Fault Clear
        19. 8.6.1.19 Identification
        20. 8.6.1.20 Temp MSB
        21. 8.6.1.21 Temp LSB
        22. 8.6.1.22 Display LED Current MSB
        23. 8.6.1.23 Display LED Current LSB
        24. 8.6.1.24 Display LED PWM MSB
        25. 8.6.1.25 Display LED PWM LSB
        26. 8.6.1.26 EEPROM Control
        27. 8.6.1.27 EEPROM Unlock Code
      2. 8.6.2 EEPROM Bit Explanations
        1. 8.6.2.1  EEPROM Register 0
        2. 8.6.2.2  EEPROM Register 1
        3. 8.6.2.3  EEPROM Register 2
        4. 8.6.2.4  EEPROM Register 3
        5. 8.6.2.5  EEPROM Register 4
        6. 8.6.2.6  EEPROM Register 5
        7. 8.6.2.7  EEPROM Register 6
        8. 8.6.2.8  EEPROM Register 7
        9. 8.6.2.9  EEPROM Register 8
        10. 8.6.2.10 EEPROM Register 9
        11. 8.6.2.11 EEPROM Register 10
        12. 8.6.2.12 EEPROM Register 11
        13. 8.6.2.13 EEPROM Register 12
        14. 8.6.2.14 EEPROM Register 13
        15. 8.6.2.15 EEPROM Register 14
        16. 8.6.2.16 EEPROM Register 15
        17. 8.6.2.17 EEPROM Register 16
        18. 8.6.2.18 EEPROM Register 17
        19. 8.6.2.19 EEPROM Register 18
        20. 8.6.2.20 EEPROM Register 19
        21. 8.6.2.21 EEPROM Register 20
        22. 8.6.2.22 EEPROM Register 21
        23. 8.6.2.23 EEPROM Register 22
        24. 8.6.2.24 EEPROM Register 23
        25. 8.6.2.25 EEPROM Register 24
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for Display Backlight
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Inductor Selection
          2. 9.2.1.2.2  Output Capacitor Selection
          3. 9.2.1.2.3  Input Capacitor Selection
          4. 9.2.1.2.4  Charge Pump Output Capacitor
          5. 9.2.1.2.5  Charge Pump Flying Capacitor
          6. 9.2.1.2.6  Diode
          7. 9.2.1.2.7  Boost Converter Transistor
          8. 9.2.1.2.8  Boost Sense Resistor
          9. 9.2.1.2.9  Power Line Transistor
          10. 9.2.1.2.10 Input Current Sense Resistor
          11. 9.2.1.2.11 Filter Component Values
            1. 9.2.1.2.11.1 Critical Components for Design
        3. 9.2.1.3 Application Performance Plots
      2. 9.2.2 Low VDD Voltage and Combined Output Mode Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Performance Plots
      3. 9.2.3 High Output Voltage Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Performance Plots
      4. 9.2.4 High Output Current Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Performance Plots
      5. 9.2.5 Three-Channel Configuration Without Serial Interface
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
        3. 9.2.5.3 Application Performance Plots
      6. 9.2.6 Solution With Minimum External Components
        1. 9.2.6.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage on pins VSENSE_N, VSENSE_P, OUT1 to OUT4, FB, SD –0.3 52 V
Voltage on pins VDD, FILTER, SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, MISO, NSS, VDDIO/EN, IF, ISENSE, ISENSE_GND, FAULT, ISET, TSENSE, C1N –0.3 6 V
Voltage on pins C1P, CPUMP, GD, SQW –0.3 12 V
Continuous power dissipation(3) Internally Limited
Ambient temperature, TA (4) –40 125 °C
Junction temperature, TJ(4) –40 150 °C
Maximum lead temperature (soldering)  See(5) °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and disengages at TJ = 135°C (typical).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX ).
(5) For detailed soldering specifications and information, refer to PowerPAD™ Thermally Enhanced Package Application Note .

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 All pins ±500
Corner pins (1,8,9,16,17,24,25,32) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage on pins VSENSE_N, VSENSE_P 3 48 V
VDD input voltage 3 5.5 V
VDDIO/EN input voltage 1.65 VDD V
Voltage on pins FILTER, ISENSE, ISENSE_GND, ISET, TSENSE, C1N 0 5.5 V
FAULT, PWM, SCLK/SCL, MOSI/SDA, NSS, IF, SYNC, MISO, VSYNC 0 VDDIO V
Voltage on pins C1P, CPUMP, GD, SQW 0 11 V
Voltage on pins OUT1 to OUT4, FB, SD 0 48 V
(1) All voltages are with respect to the potential at the GND pins.

7.4 Thermal Information

THERMAL METRIC(1) LP8860 UNIT
HLQFP PowerPAD (VLP)
32 PINS
RθJA Junction-to-ambient thermal resistance(2) 36.0 °C/W
RθJCtop Junction-to-case (top) thermal resistance 23.3 °C/W
RθJB Junction-to-board thermal resistance 15.5 °C/W
ψJT Junction-to-top characterization parameter 3.2 °C/W
ψJB Junction-to-board characterization parameter 15.5 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 1.6 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.5 Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IQ Shutdown supply current for VDD Device disabled, VDDIO/EN = 0 V 1 5 μA
Active supply current for VDD,
VDD = 5 V		 Backlight enabled (no load), boost enabled, PLL and CP disabled, DRV_LED_BIAS_CTRL[1:0] = 10 , boost ƒSW = 300 kHz 2.5 6 mA
Backlight enabled (no load), boost enabled, CP disabled, ƒPLL = 10 MHz, DRV_LED_BIAS_CTRL[1:0] = 11, boost ƒSW = 400 kHz 4.5 15
VVDD_POR_R Power-on reset rising threshold 2.2 V
VVDD_POR_F Power-on reset falling threshold 1.1
TTSD Thermal shutdown threshold 150 165 180 °C
TTSD_THR Thermal shutdown hysteresis 30
INTERNAL OSCILLATOR
ƒOSC Frequency 10 MHz
Frequency accuracy –7% 7%
(1) All voltages are with respect to the potential at the GND pins.
(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis.

7.6 Current Sinks Electrical Characteristics

Limits apply over the full ambient temperature range –40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33 μF electrolytic, COUT = 2 × 10 μF ceramic and 33 μF electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILEAKAGE Leakage current Outputs OUT1 to OUT4, VOUT = 48 V 0.1 1 µA
IMAX Maximum source current OUT1 to OUT4 150 mA
IOUT Output current accuracy IOUT = 150 mA −3% 3%
IMATCH Output current matching(1) IOUT = 150 mA, 100% brightness 0.5% 2%
ƒLED_PWM LED PWM output frequency for display mode PWM_FREQ[3:0] = 0000b
PWM_FREQ[3:0] = 1111b		 4883
39 063		 Hz
ƒPWM PWM input frequency BRT_MODE[1:0] = 00, 01 and 10 100 500 Hz
tPWM MIN Minimum on and off time for PWM input 400 ns
IDIM Dimming ratio (input resolution) External 100 Hz PWM 13 000:1
SPI or I2C control 16 bit
PWMRES PWM output resolution, PWM control for BRT_MODE[1:0] = 00, 01, and 10 (without dithering) ƒLED_PWM = 5 kHz, ƒOSC = 5 MHz 10 bits
ƒLED_PWM= 10 kHz, ƒOSC = 5 MHz 9
ƒLED_PWM = 20 kHz, ƒOSC = 5 MHz 8
ƒLED_PWM = 40 kHz, ƒOSC = 5 MHz 7
ƒLED_PWM = 5 kHz, ƒOSC = 40 MHz 13
ƒLED_PWM = 10 kHz, ƒOSC = 40 MHz 12
ƒLED_PWM = 20 kHz, ƒOSC = 40 MHz 11
ƒLED_PWM = 40 kHz, ƒOSC = 40 MHz 10
ΔIOUT Individual output current adjustment range DRV_OUTx_CORR[3:0] = 1111 –7.4%
DRV_OUTx_CORR[3:0] = 0000 6.5%
VSAT Saturation voltage(2) IOUT = 150 mA 0.5 0.75 V
VSHORT_FAULT_THR LED short detection threshold DRV_LED_FAULT_THR[1:0] = 00 3.6 V
DRV_LED_FAULT_THR[1:0] = 01 3.6
DRV_LED_FAULT_THR[1:0] = 10 6.9
DRV_LED_FAULT_THR[1:0] = 11 10.6
(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note that some manufacturers have different definitions in use.
(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.7 Boost Converter Characteristics

Limits apply over the full ambient temperature range – 40°C ≤ TA ≤ +125°C. Unless otherwise specified: VDD = 3.3 V, VIN = 12 V, EN/VDDIO = 3.3 V, L = 22 μH, CIN = 2 × 10 μF ceramic and 33-μF electrolytic, COUT = 2 × 10 μF ceramic and 33-μF electrolytic, CVDD = 1 μF, CCPUMP = 10 μF, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILOAD Maximum continuous load current VIN = 6 V, VBOOST = 48 V (ƒSW = 303 kHz) 600 mA
VIN = 3 V, VBOOST = 30 V (ƒSW = 1.1 MHz) 150
VIN = 3 V, VBOOST = 30 V (ƒSW = 2.2 MHz) 100
VOUT/VIN Conversion ratio 10
ƒSW Switching frequency (central frequency if spread spectrum is enabled) BOOST_FREQ = 000
BOOST_FREQ = 001
BOOST_FREQ = 010
BOOST_FREQ = 011
BOOST_FREQ = 100
BOOST_FREQ = 101
BOOST_FREQ = 110
BOOST_FREQ = 111 		–7% 100
200
303
400
629
800
1100
2200		 7% kHz
tBOOST START-UP Start-up time (1) 50 ms
IMAX SW current limit RSENSE = 25 mΩ A
BOOST_IMAX_SEL=000
BOOST_IMAX_SEL=001
BOOST_IMAX_SEL=010
BOOST_IMAX_SEL=011
BOOST_IMAX_SEL=100
BOOST_IMAX_SEL=101
BOOST_IMAX_SEL=110
BOOST_IMAX_SEL=111		 2
3
4
5
6
7
8
9
VGD Gate driver output voltage 0 11 V
IGD_SOURCE_PEAK Gate driver peak current, sourcing BOOST_DRIVER_SIZE[1:0] = 11
BOOST_GD_VOLT = 1
VDD= 5 V, VCPUMP = 10 V
FET SQ4850EY 		1.7 A
IGD_SINK_PEAK Gate driver peak current, sinking 1.5
(1) Start-up time is measured from the moment the boost is activated until the VOUT crosses 90% of its initial voltage value.

7.8 Logic Interface Characteristics

VDDIO/EN = 1.65 V to VDD, VDD = 3.3 V unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUT VDDIO/EN
VIL Input low level 0.4 V
VIH Input high level 1.2
II Input current −1 1 µA
LOGIC INPUT SYNC, VSYNC, PWM, SCLK/SCL, MOSI/SDA, NSS, IF
VIL Input low level 0.2 × VDDIO/EN V
VIH Input high level 0.8 × VDDIO/EN
II Input current −1 1 μA
LOGIC OUTPUT FAULT
VOL Output low level I = 3 mA 0.3 0.5 V
ILEAKAGE Output leakage current V = 5.5 V 1 μA
LOGIC OUTPUT MISO
VOL Output low level IOUT = 3 mA 0.3 0.5 V
VOH Output high level IOUT = –2 mA 0.7 × VDDIO/EN 0.9 × VDDIO/EN
IL Output leakage current 1 μA
LOGIC OUTPUTS SDA
VOL Output low level I = 3 mA 0.3 0.5 V
ILEAKAGE Output leakage current V = 5.5 V 1 μA

7.9 VIN Undervoltage Protection (VIN_UVLO)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO VIN UVLO threshold voltage UVLO[1:0] = 00 Disabled V
UVLO[1:0] = 01 2.64 3 3.36
UVLO[1:0] = 10 4.4 5 5.6
UVLO[1:0] = 11 7.04 8 8.96

7.10 VDD Undervoltage Protection (VDD_UVLO)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVDD_UVLO VDD UVLO threshold voltage VDD_UVLO_LEVEL = 0 2.5 V
VDD_UVLO_LEVEL = 1 3
VHYST VDD UVLO hysteresis 50 mV

7.11 VIN Overvoltage Protection (VIN_OVP)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOVP VIN OVP threshold voltage OVP[1:0] = 00 Disabled V
OVP[1:0] = 01 6.16 7 7.84
OVP[1:0] = 10 9.68 11 12.32
OVP[1:0] = 11 19.8 22.5 25.2

7.12 VIN Overcurrent Protection (VIN_OCP)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOCP VIN current protection limit with RISENSE = 20 mΩ, VIN = 12 V
See(1)		 PL_SD_LEVEL[1:0] = 10 6 A
PL_SD_LEVEL[1:0] = 11 8

7.13 Power-Line FET Control Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IL,VSENSE_P VSENSE_P pin leakage current VSENSE_P = 48 V 0.1 3 µA
IL,VSENSE_N VSENSE_N pin leakage current VSENSE_N = 48 V
IL,SD SD pin leakage current VSD = 48 V
ISD PFET Pulldown current for power-line
p-FET, NMOS_PLFET_EN=0 		PL_SD_SINK_LEVEL = 00
PL_SD_SINK_LEVEL = 01
PL_SD_SINK_LEVEL = 10
PL_SD_SINK_LEVEL = 11		 55
110
220
440		 µA

7.14 External Temp Sensor Control Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RTEMP_HIGH TSENSE high level resistance value EXT_TEMP_LEVEL_HIGH[3:0] = 0000
EXT_TEMP_LEVEL_HIGH[3:0] = 0001
EXT_TEMP_LEVEL_HIGH[3:0] = 0010
EXT_TEMP_LEVEL_HIGH[3:0] = 0011
EXT_TEMP_LEVEL_HIGH[3:0] = 0100
EXT_TEMP_LEVEL_HIGH[3:0] = 0101
EXT_TEMP_LEVEL_HIGH[3:0] = 0110
EXT_TEMP_LEVEL_HIGH[3:0] = 0111
EXT_TEMP_LEVEL_HIGH[3:0] = 1000
EXT_TEMP_LEVEL_HIGH[3:0] = 1001
EXT_TEMP_LEVEL_HIGH[3:0] = 1010
EXT_TEMP_LEVEL_HIGH[3:0] = 1011
EXT_TEMP_LEVEL_HIGH[3:0] = 1100
EXT_TEMP_LEVEL_HIGH[3:0] = 1101
EXT_TEMP_LEVEL_HIGH[3:0] = 1110
EXT_TEMP_LEVEL_HIGH[3:0] = 1111 		79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87 		kΩ
RTEMP_LOW TSENSE low-level resistance value EXT_TEMP_LEVEL_LOW[3:0] = 0000
EXT_TEMP_LEVEL_LOW[3:0] = 0001
EXT_TEMP_LEVEL_LOW[3:0] = 0010
EXT_TEMP_LEVEL_LOW[3:0] = 0011
EXT_TEMP_LEVEL_LOW[3:0] = 0100
EXT_TEMP_LEVEL_LOW[3:0] = 0101
EXT_TEMP_LEVEL_LOW[3:0] = 0110
EXT_TEMP_LEVEL_LOW[3:0] = 0111
EXT_TEMP_LEVEL_LOW[3:0] = 1000
EXT_TEMP_LEVEL_LOW[3:0] = 1001
EXT_TEMP_LEVEL_LOW[3:0] = 1010
EXT_TEMP_LEVEL_LOW[3:0] = 1011
EXT_TEMP_LEVEL_LOW[3:0] = 1100
EXT_TEMP_LEVEL_LOW[3:0] = 1101
EXT_TEMP_LEVEL_LOW[3:0] = 1110
EXT_TEMP_LEVEL_LOW[3:0] = 1111 		79.67
43.35
29.77
22.67
18.30
15.34
13.21
11.60
10.34
9.32
8.49
7.79
7.20
6.69
6.25
5.87 		kΩ
RTS_FLOAT TSENSE maximum resistance (missing resistor fault value) 2 MΩ

7.15 I2C Serial Bus Timing Parameters (SDA, SCLK)

See Figure 1.
MIN NOM MAX UNIT
ƒSCLK Clock frequency 400 kHz
1 Hold time (repeated) START Condition 0.6 µs
2 Clock low time 1.3 25000 µs
3 Clock high time 600 ns
4 Set-up time for a repeated START condition 600 ns
5 Data hold time 50 ns
6 Data setup time 100 ns
7 Rise Time of SDA and SCL 20+0.1xCb 300 ns
8 Fall Time of SDA and SCL 15+0.1xCb 300 ns
9 Set-up time for STOP condition 600 ns
10 Bus free time between a STOP and a START Condition 1.3 µs
Cb Capacitive load parameter for each bus line
load of 1 pF corresponds to 1 ns.		 10 200 ns

7.16 SPI Timing Requirements

See Figure 2.
MIN NOM MAX UNIT
1 Cycle time 70 ns
2 Enable lead time 35 ns
3 Enable lag time 35 ns
4 Clock low time 35 ns
5 Clock high time 35 ns
6 Data setup time 20 ns
7 Data hold time 20 ns
8 Disable time 10 ns
9 Data valid 29 ns
10 NSS inactive time 700 ns
Cb Bus capacitance 5 40 pF
LP8860-Q1 30162698.png Figure 1. I2C Timing
LP8860-Q1 SPI_td_snvsa21.gif Figure 2. SPI Timing Diagram

7.17 Typical Characteristics

Unless otherwise specified: L= 22 µH (IHLP-5050FDER220M5A), CIN = 2 × 10-µF ceramic and 33 µF electrolytic, COUT = 2 × 10-µF ceramic and 33-µF electrolytic, Q = IPD25N06S4L-30-ND, D = SS5P10-M3/86A, VDD = 5 V, charge pump disabled, T = 25°C
LP8860-Q1 C001_SNVSA21.png
ƒSW = 303 kHz 8 LEDs/string 150 mA/string
4 strings
Figure 3. System Efficiency
LP8860-Q1 C007_SNVSA21.png
ƒSW = 303 kHz Adaptive voltage control off
Figure 5. Boost Maximum Output Current
LP8860-Q1 C003_SNVSA21.png
ƒSW = 303 kHz 8 LEDs/string 150 mA/string
4 strings Phase shift 90º ƒLED_PWM = 4.9 kHz
Figure 7. Boost Ripple
LP8860-Q1 C004_SNVSA21.png
ƒSW = 2.2 MHz 8 LEDs/string 100 mA/string
4 strings
Figure 4. System Efficiency
LP8860-Q1 C006_SNVSA21.png
Figure 6. LED Current vs Headroom Voltage
LP8860-Q1 C005_SNVSA21.png
fSW = 2.2 MHz 8 LEDs/string 100 mA/string
4 strings Phase shift 90º fLED_PWM= 4.9 kHz
Figure 8. Boost Ripple