SNVSA50C August   2015  – May 2017 LP8861-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Internal LDO Electrical Characteristics
    7. 7.7  Protection Electrical Characteristics
    8. 7.8  Power Line FET Control Electrical Characteristics
    9. 7.9  Current Sinks Electrical Characteristics
    10. 7.10 PWM Brightness Control Electrical Characteristics
    11. 7.11 Boost/SEPIC Converter Characteristics
    12. 7.12 Logic Interface Characteristics
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Integrated Boost/SEPIC Converter
      2. 8.3.2 Internal LDO
      3. 8.3.3 LED Current Sinks
        1. 8.3.3.1 Current Sink Configuration
        2. 8.3.3.2 Current Setting
        3. 8.3.3.3 Brightness Control
      4. 8.3.4 Power-Line FET Control
      5. 8.3.5 LED Current Dimming With External Temperature Sensor
      6. 8.3.6 Protection and Fault Detection
        1. 8.3.6.1 Adaptive Boost Control and Functionality of LED Fault Comparators
        2. 8.3.6.2 Overview of the Fault/Protection Schemes
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device States
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for 4 LED Strings
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Inductor Selection
          2. 9.2.1.2.2 Output Capacitor Selection
          3. 9.2.1.2.3 Input Capacitor Selection
          4. 9.2.1.2.4 LDO Output Capacitor
          5. 9.2.1.2.5 Diode
          6. 9.2.1.2.6 Power Line Transistor
          7. 9.2.1.2.7 Input Current Sense Resistor
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High Output Current Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 SEPIC Mode Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Diode
          2. 9.2.3.2.2 Inductor
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Application with Temperature Based LED Current De-rating
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
      1. 13.1.2 Tape and Reel Information
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage on pins VIN, VSENSE_N, SD, SW, FB –0.3 50 V
OUT1…OUT4 –0.3 45
LDO, SYNC, FSET, ISET, TSENSE, TSET, PWM, VDDIO/EN, FAULT –0.3 5.5
Continuous power dissipation(3) Internally Limited
Ambient temperature range, TA(4) –40 125 ºC
Junction temperature range, TJ(4) –40 150 ºC
Maximum lead temperature (soldering)  See(5) ºC
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical) and disengages at TJ = 145°C (typical).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 150°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
(5) For detailed soldering specifications and information, refer to the PowerPAD™ Thermally Enhanced Package Application Note (SLMA002).

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 Other pins ±500
Corner pins (1,10,11,20) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage on pins VIN 4.5 45 V
VSENSE_N, SD, SW 0 45
OUT1…OUT4 0 40
FB, FSET, LDO, ISET, TSENSE, TSET, VDDIO/EN, FAULT 0 5.25
SYNC, PWM 0 VDDIO/EN
(1) All voltages are with respect to the potential at the GND pins.

7.4 Thermal Information

THERMAL METRIC(1) LP8861-Q1 UNIT
PWP (TSSOP)
20 PINS
RθJA Junction-to-ambient thermal resistance(2) 44.2 °C/W
RθJCtop Junction-to-case (top) thermal resistance 26.5 °C/W
RθJB Junction-to-board thermal resistance 22.4 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 22.2 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

7.5 Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IQ Standby supply current Device disabled, VVDDIO/EN = 0 V, VIN = 12 V 4.5 20 μA
Active supply current VIN = 12 V, VBOOST= 26 V, output current 80 mA/channel, ƒSW= 300 kHz 5 12 mA
VPOR_R Power-on reset rising threshold LDO pin voltage. Output of the internal LDO or an external supply input (VDD). 2.7 V
VPOR_F Power-on reset falling threshold LDO pin voltage. Output of the internal LDO or an external supply input (VDD). 1.5 V
TTSD Thermal shutdown threshold 150 165 175 °C
TTSD_THR Thermal shutdown hysteresis 20 °C
(1) All voltages are with respect to the potential at the GND pins.
(2) Min and Max limits are specified by design, test, or statistical analysis.

7.6 Internal LDO Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLDO Output voltage VIN = 12 V 4.15 4.3 4.45 V
VDR Dropout voltage External current load 5 mA 120 220 430 mV
ISHORT Short circuit current 50 mA
IEXT_MAX Maximum current for external load 5 mA

7.7 Protection Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOVP VIN OVP threshold voltage 41 42 44 V
IOCP VIN OCP current RSENSE = 50 mΩ 2.7 3.2 3.7 A
VUVLO VIN UVLO 4.0 V
VUVLO_HYST VIN UVLO hysteresis 100 mV
LED short detection threshold 5.6 6 7 V

7.8 Power Line FET Control Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSENSE_N pin leakage current VVSENSE_N = 45 V 0.1 3 µA
SD leakage current VSD = 45 V 0.1 3 µA
SD pulldown current 185 230 283 µA

7.9 Current Sinks Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ILEAKAGE Leakage current Outputs OUT1 to OUT4, VOUTx = 45 V 0.1 5 µA
IMAX Maximum current OUT1 to OUT4 100 mA
IOUT Output current accuracy IOUT = 100 mA −5% 5%
IMATCH Output current matching(1) IOUT = 100 mA, PWM duty = 100% 1% 3.5%
VSAT Saturation voltage(2) IOUT = 100 mA, VLDO = 4.3 V 0.4 0.7 V
(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current sinks on the part (OUT1 to OUT4), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Matching number is calculated: (MAX-MIN)/AVG. The typical specification provided is the most likely norm of the matching figure for all parts. LED current sinks were characterized with 1-V headroom voltage. Note that some manufacturers have different definitions in use.
(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at 1 V.

7.10 PWM Brightness Control Electrical Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ƒPWM Recommended PWM input frequency 100 20 000 Hz
tON/OFF Minimum ON/OFF time(1) 0.5 µs
(1) This specification is not ensured by ATE.

7.11 Boost/SEPIC Converter Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
Unless otherwise specified: VIN = 12 V, VVDDIO/EN = 3.3 V, L = 22 μH, CIN = 2 × 10-μF ceramic and 33-μF electrolytic,
COUT = 2 × 10-μF ceramic and 33-μF electrolytic, D = NRVB460MFS, ƒSW = 300 kHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 4.5 40 V
VOUT Output voltage 10 45 V
ƒSW_MIN Minimum switching frequency (central frequency if spread spectrum is enabled) Defined by RFSET resistor 300 kHz
ƒSW_MAX Maximum switching frequency (central frequency if spread spectrum is enabled) 2200 kHz
VOUT/VIN Conversion ratio 10
TOFF Minimum switch OFF time(1) ƒSW ≥ 1.15 MHz 55 ns
ISW_MAX SW current limit 1.8 2 2.2 A
RDSon FET RDSon Pin-to-pin 240 400 mΩ
ƒSYNC External SYNC frequency 300 2200 kHz
tSYNC_ON_MIN External SYNC minimum ON time(1) 150 ns
tSYNC_OFF_MIN External SYNC minimum OFF time(1) 150 ns
(1) This specification is not ensured by ATE.

7.12 Logic Interface Characteristics

TJ = −40°C to +125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUT VDDIO/EN
VIL Input low level 0.4 V
VIH Input high level 1.65 V
II Input current −1 5 30 µA
LOGIC INPUTS SYNC, PWM
VIL Input low level 0.2 × VVDDIO/EN V
VIH Input high level 0.8 × VVDDIO/EN
II Input current −1 1 μA
LOGIC OUTPUT FAULT
VOL Output low level Pullup current 3 mA 0.3 0.5 V
ILEAKAGE Output leakage current V = 5.5 V 1 μA

7.13 Typical Characteristics

Unless otherwise specified: D = NRVB460MFS, T = 25°C.
LP8861-Q1 C001_SNVSA50.png
ƒSW = 300 kHz L = 33 μH DC Load (PWM = 100%)
CIN and COUT = 33 µF + 2 × 10 µF (ceramic)
Figure 1. Maximum Boost Output Current
LP8861-Q1 C003_SNVSA50.png
ƒSW = 1.5 MHz L = 8.2 μH DC Load (PWM = 100%)
CIN and COUT = 2 × 10 µF (ceramic)
Figure 3. Maximum Boost Output Current
LP8861-Q1 C005_SNVSA50.png
Figure 5. LED Current vs RISET
LP8861-Q1 C013_SNVSA50.png
Figure 7. LED Current Sink Matching
LP8861-Q1 C002_SNVSA50.png
ƒSW = 800 kHz L = 15 μH DC Load (PWM = 100%)
CIN and COUT = 2 × 10 µF (ceramic)
Figure 2. Maximum Boost Output Current
LP8861-Q1 C004_SNVSA50.png
ƒSW = 2.2 MHz L = 4.7 μH DC Load (PWM = 100%)
CIN and COUT = 2 × 10 µF (ceramic)
Figure 4. Maximum Boost Output Current
LP8861-Q1 C009_SNVSA50.png
Figure 6. Boost Switching Frequency ƒSW vs RFSET
LP8861-Q1 C014_SNVSA50.png
RISET = 24 kΩ
Figure 8. LED Current Sink Saturation Voltage