Examples of a proper layout for boost topolgy,
buck-boost topology and buck topology of LP885 family is shown
below.
- Creating a large GND plane for good electrical and thermal performance is important.
- The IN and GND traces should be as wide as possible to reduce trace impedance. Wide traces have the additional advantage of providing excellent heat dissipation.
- Thermal vias can be used to connect the top-side GND plane to additional printed-circuit board (PCB) layers for heat dissipation and grounding.
- The input capacitors must be located as close as possible to the IN pin and the GND pin.
- The VCC capacitor should be placed as close as possible to VCC pin to ensure
stable LDO output voltage.
- The SW trace must be kept as short as possible to reduce parasitic inductance
and thereby reduce transient voltage spikes. Short SW trace also reduces
radiated noise and EMI.
- Do not allow switching current to flow under the device.
- The routing of CSN and CSP traces are recommended to be in parallel and kept as
short as possible and placed away from the high-voltage switching trace and the
ground shield.
- The compensation capacitor must be placed as close as possible to COMP pin so
as to prevent oscillation and system instability.