SLVSH05 November 2023 LP8865U-Q1 , LP8865V-Q1 , LP8865W-Q1 , LP8865X-Q1 , LP8865Y-Q1 , LP8865Z-Q1
PRODUCTION DATA
The PWM dimming mode is enabled when the ADIM/HD input pin is always high and the PWM/EN input pin is configured by a PWM input signal. Device supports PWM input signals with ultra-narrow pulse width down to 200 ns in PWM dimming mode. The PWM output duty cycle can be changed in the opposite direction only when PWM input duty cycle changes by more than 0.38%.
In PWM dimming mode, when the PWM input signal at the PWM pin turns from low to high, the internal NMOS FET starts switching and the inductor current rises to the determined value. The LED current is then regulated at the determined value as long as the PWM input signal stays high. When the PWM input signal turns from high to low, the internal FET is turned off causing the inductor current falling to zero. The internal FET maintains off and the LED current stays zero if the PWM input signal stays low.