SNVSBD1B August 2020 – May 2024 LP8866S-Q1
PRODUCTION DATA
If during LP8866S-Q1 device initialization, the factory default configuration for registers, options and trim bits are not corrected loaded from memory, LP8866S-Q1 keeps operating normally, unless other fault criteria is triggered. The CRCERR_STATUS fault bit are set in the SUPPLY_FAULT_STATUS register and the INT pin are triggered.