SNOSB14E August   2009  – July 2024 LPV521

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input Stage
      2. 6.4.2 Output Stage
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Capacitive Load
      2. 7.1.2 EMI Suppression
    2. 7.2 Typical Applications
      1. 7.2.1 60Hz Twin T-Notch Filter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Portable Gas Detection Sensor
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 High-Side Battery Current Sensing
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • P|8
  • DCK|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.3.2 Detailed Design Procedure

The theoretical output voltage of the circuit is VOUT = [ (RSENSE × R3) / R1 ] × ICHARGE. In reality, however, as a result of the finite current gain of the transistor (β), the current that travels through R3 is not ICHARGE. Instead, R3 is α × ICHARGE or β / ( β+1) × ICHARGE. A Darlington pair can be used to increase the β and performance of the measuring circuit.

Using the components shown in Figure 7-7 results in VOUT ≈ 4000Ω × ICHARGE. This result is needed to amplify a 1mA ICHARGE to near full-scale of an analog-to-digital converter (ADC) with VREF at 4.1V. A resistor, R2 is used at the noninverting input of the amplifier, with the same value as R1 to minimize offset voltage.

Selecting values per Figure 7-7 limits the current traveling through the R1 – Q1 – R3 leg of the circuit to under 1µA, which is on the same order as the LPV521 supply current. Increasing resistors R1, R2, and R3 decreases the measuring circuit supply current and extends battery life.

Decreasing RSENSE minimizes error due to resistor tolerance; however, this decrease also decreases VSENSE = ICHARGE × RSENSE, and in turn, the amplifier offset voltage has a more significant contribution to the total error of the circuit. With the components shown in Figure 7-7, the measurement circuit supply current can be kept below 1.5µA and measure 100µA to 1mA.