SNOSB14E August   2009  – July 2024 LPV521

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input Stage
      2. 6.4.2 Output Stage
  8. Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Capacitive Load
      2. 7.1.2 EMI Suppression
    2. 7.2 Typical Applications
      1. 7.2.1 60Hz Twin T-Notch Filter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Portable Gas Detection Sensor
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 High-Side Battery Current Sensing
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • P|8
  • DCK|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Driving Capacitive Load

The LPV521 is internally compensated for stable unity gain operation, with a 6.2kHz, typical gain bandwidth. However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a capacitive load placed at the output of an amplifier along with the amplifier output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response is underdamped, and causes peaking in the transfer. When there is too much peaking, the op amp can start oscillating.

LPV521 Resistive Isolation of Capacitive LoadFigure 7-1 Resistive Isolation of Capacitive Load

To drive heavy capacitive loads, use an isolation resistor, RISO, as in Figure 7-1. By using this isolation resistor, the capacitive load is isolated from the amplifier output. The larger the value of RISO, the more stable the amplifier. If the value of RISO is sufficiently large, the feedback loop is stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive.

Table 7-1 shows the recommended minimum RISO values for a 5V supply. Figure 7-2 shows the typical response obtained with the CL = 50pF and RISO = 154kΩ. The other values of RISO in Table 7-1 are chosen to achieve similar dampening at the respective capacitive loads. Notice that for the LPV521 with larger a CL, a smaller RISO can be used for stability. However, for a given CL, a larger RISO provides a more damped response. For capacitive loads of 20pF and less, no isolation resistor is needed.

Table 7-1 Recommended Minimum RISO Values for a 5V Supply
CL RISO
0pF to 20pF Not needed
50pF 154kΩ
100pF 118kΩ
500pF 52.3kΩ
1nF 33.2kΩ
5nF 17.4kΩ
10nF 13.3kΩ
LPV521 Step ResponseFigure 7-2 Step Response