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  • LPV811/LPV812 Precision 425 nA Nanopower Operational Amplifiers

    • SNOSD33B November   2016  – November 2016 LPV811 , LPV812

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • LPV811/LPV812 Precision 425 nA Nanopower Operational Amplifiers
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Nanopower CO Sensor
    2. 3.2 LPV812 Offset Voltage Distribution Front page O2 Sens circuit to Vos Disty Graph
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Negative-Rail Sensing Input
      2. 7.4.2 Rail to Rail Output Stage
      3. 7.4.3 Design Optimization for Nanopower Operation
      4. 7.4.4 Driving Capacitive Load
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Three Terminal CO Gas Sensor Amplifier
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
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    • MPDS028E
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Orderable Information
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DATA SHEET

LPV811/LPV812 Precision 425 nA Nanopower Operational Amplifiers

1 Features

  • Nanopower Supply Current: 425 nA/channel
  • Offset Voltage: 300 µV (max)
  • TcVos: 1 µV/°C
  • Gain-Bandwidth: 8 kHz
  • Unity-Gain Stable
  • Low Input Bias Current : 100 fA
  • Wide Supply Range: 1.6 V to 5.5 V
  • Rail-to-Rail Output
  • No Output Reversals
  • EMI Protection
  • Temperature Range: –40°C to 125°C
  • Industry Standard Packages:
    • Single in 5-pin SOT-23
    • Dual in 8-pin VSSOP

2 Applications

  • CO and O2 Gas Detectors (TIDA-0756)
  • PIR Motion Detectors
  • Current Sensing
  • Thermostats
  • IoT Remote Sensors
  • Active RFID Readers and Tags
  • Portable Medical Equipment

3 Description

The LPV811 (single) and LPV812 (dual) are a ultra-low-power precision operational amplifier family for “Always ON” sensing applications in battery powered wireless and low power wired equipment. With 8 kHz of bandwidth from 425 nA of quiescent current and a trimmed offset voltage to under 300µV, the LPV81x amplifiers provide the required precision while minimizing power consumption in equipment such as gas detectors and portable electronic devices where operational battery-life is critical.

In addition to being ultra-low-power, the LPV81x amplifiers have CMOS input stages with fempto-amp bias currents for impedance source applications. The LPV81x amplifiers also feature a negative-rail sensing input stage and a rail-to-rail output stage that swings within millivolts of the rails, maintaining the widest dynamic range possible. EMI protection is designed into the LPV81x in order to reduce system sensitivity to unwanted RF signals from mobile phones, WiFi, radio transmitters, and tag readers.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
LPV811 SOT-23 (5) 2.90 mm x 1.60 mm
LPV812 VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.

LPV8xx Family of Nanopower Amplifiers

PART NUMBER CHANNELS SUPPLY
CURRENT
(Typ/Ch)		 OFFSET
VOLTAGE
(Max)
LPV801 1 500 nA 3.5 mV
LPV802 2 320 nA 3.5 mV
LPV811 1 450 nA 370 µV
LPV812 2 425 nA 300 µV

3.1 Nanopower CO Sensor

LPV811 LPV812 O2_Sens_Ckt.gif

3.2 LPV812 Offset Voltage Distribution

LPV811 LPV812 812B_Dist_3p3.png

4 Revision History

Changes from A Revision (October 2016) to B Revision

  • Added family upsell table to front page Go
  • Changed Front page O2 Sens circuit to Vos Disty Graph Go
  • Deleted larger family upsell table Go
  • Deleted LPV811 preview "preliminary spec" table note. Go
  • Added separate LPV811 CMRR Specification. Go
  • Added offset distribution graphs Go

Changes from * Revision (August 2016) to A Revision

  • Changed Product Preview to Production Data. Go

5 Pin Configuration and Functions

LPV811 5-Pin SOT-23
DBV Package
Top View
LPV811 LPV812 po_333_sot23_bos351.gif
LPV812 8-Pin VSSOP
DGK Package
Top View
LPV811 LPV812 po_2333_so_msop_bos351.gif

Pin Functions: LPV811 DBV

PIN TYPE DESCRIPTION
NAME NUMBER
OUT 1 O Output
-IN 4 I Inverting Input
+IN 3 I Non-Inverting Input
V- 2 P Negative (lowest) power supply
V+ 5 P Positive (highest) power supply

Pin Functions: LPV812 DGK

PIN TYPE DESCRIPTION
NAME NUMBER
OUT A 1 O Channel A Output
-IN A 2 I Channel A Inverting Input
+IN A 3 I Channel A Non-Inverting Input
V- 4 P Negative (lowest) power supply
+IN B 5 I Channel B Non-Inverting Input
-IN B 6 I Channel B Inverting Input
OUT B 7 O Channel B Output
V+ 8 P Positive (highest) power supply

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, Vs = (V+) - (V-) –0.3 6 V
Input pins Voltage (2) (3) Common mode (V-) - 0.3 (V+) + 0.3 V
Differential (V-) - 0.3 (V+) + 0.3 V
Input pins Current -10 10 mA
Output short current (4) Continuous Continuous
Storage temperature, Tstg –65 150 °C
Junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Not to exceed -0.3V or +6.0V on ANY pin, referred to V-
(3) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current-limited to 10 mA or less.
(4) Short-circuit to Vs/2, one amplifier per package. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions. Pins listed as ±750 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage (V+ – V–) 1.6 5.5 V
Specified temperature -40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LPV811
DBV
(SOT-23)
5 PINS		 LPV812
DGK
(VSSOP)
8 PINS		 UNIT
θJA Junction-to-ambient thermal resistance 177.4 177.6 ºC/W
θJCtop Junction-to-case (top) thermal resistance 133.9 68.8
θJB Junction-to-board thermal resistance 36.3 98.2
ψJT Junction-to-top characterization parameter 23.6 12.3
ψJB Junction-to-board characterization parameter 35.7 96.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TA = 25°C, VS = 1.8 V to 5 V, VCM = VOUT = VS/2, and RL≥ 10 MΩ to VS / 2, unless otherwise noted .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage, LPV811 VS = 1.8V and 3.3V, VCM = V- ±60 ±370 µV
Input offset voltage, LPV812 VS = 1.8V and 3.3V, VCM = V- ±55 ±300 µV
ΔVOS/ΔT Input offset drift VCM = V- TA = –40°C to 125°C ±1 µV/°C
PSRR Power-supply rejection ratio VS = 1.8V to 3.3V,  VCM = V- ±1.6 ±60 µV/V
INPUT VOLTAGE RANGE
VCM Common-mode voltage range VS = 3.3V 0 2.4 V
CMRR Common-mode rejection ratio, LPV811 (V–) ≤ VCM ≤ (V+) – 0.9 V, VS = 3.3V 77 95 dB
Common-mode rejection ratio, LPV812 (V–) ≤ VCM ≤ (V+) – 0.9 V, VS = 3.3V 80 98 dB
INPUT BIAS CURRENT
IB Input bias current VS = 1.8V ±100 fA
IOS Input offset current VS = 1.8V ±100 fA
INPUT IMPEDANCE
Differential 7 pF
Common mode 3 pF
NOISE
En Input voltage noise ƒ = 0.1 Hz to 10 Hz 6.5 µVp-p
en Input voltage noise density ƒ = 100 Hz 340 nV/√Hz
ƒ = 1 kHz 420
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.3 V ≤ VO ≤ (V+) – 0.3 V, RL = 100 kΩ 120 dB
OUTPUT
VOH Voltage output swing from positive rail VS = 1.8V, RL = 100 kΩ to V+/2 10 3.5 mV
VOL Voltage output swing from negative rail VS = 1.8V, RL = 100 kΩ to V+/2 2.5 10
ISC Short-circuit current VS = 3.3V, Short to VS/2 4.7 mA
ZO Open loop output impedance ƒ = 1 KHz, IO = 0 A 90 kΩ
FREQUENCY RESPONSE
GBP Gain-bandwidth product CL = 20 pF, RL = 10 MΩ, VS = 5V 8 kHz
SR Slew rate (10% to 90%) G = 1, Rising Edge, CL = 20 pF, VS = 5V 2 V/ms
G = 1, Falling Edge, CL = 20 pF, VS = 5V 2.1
POWER
SUPPLY
IQ Quiescent Current, LPV811 VCM = V-, IO = 0, VS = 3.3V 450 540 nA
Quiescent Current,
Per Channel, LPV812		 VCM = V-, IO = 0, VS = 3.3V 425 495

6.6 Typical Characteristics

at TA = 25°C, RL = 10MΩ to VS/2 ,CL = 20pF, VCM = VS / 2V unless otherwise specified.
LPV811 LPV812 811_Dist_1p8.png
VS = 1.8V LPV811
TA = 25°C VCM = V- RL=No Load
Figure 1. Offset Distribution of LPV811
LPV811 LPV812 812A_Dist_1p8.png
VS = 1.8V LPV812, Channel A
TA = 25°C VCM = V- RL=No Load
Figure 3. Offset Distribution of LPV812, CH A
LPV811 LPV812 812A_Dist_1p8.png
VS =1.8V LPV812, Channel B
TA = 25°C VCM = V- RL=No Load
Offset Distribution of LPV812, CH B
LPV811 LPV812 TG_811_Iq_Vs_Vs.png
VCM = V- LPV811 RL=No Load
Figure 6. Supply Current vs. Supply Voltage, LPV811
LPV811 LPV812 TG_Vos_Vcm_1p8.png
VS= 1.8V RL= 10MΩ
Figure 8. Typical Offset Voltage vs. Common Mode Voltage
LPV811 LPV812 TG_812_Vos_Vcm_5V.png
VS= 5V RL= 10MΩ
Figure 10. Typical Offset Voltage vs. Common Mode Voltage
LPV811 LPV812 IB_VCM_1p8V_m40.png
VS= 1.8V TA = -40°C
Figure 12. Input Bias Current vs. Common Mode Voltage
LPV811 LPV812 IB_VCM_1p8V_25C.png
VS= 1.8V TA = 25°C
Figure 14. Input Bias Current vs. Common Mode Voltage
LPV811 LPV812 IB_VCM_1p8V_125C.png
VS= 1.8V TA = 125°C
Figure 16. Input Bias Current vs. Common Mode Voltage
LPV811 LPV812 TG_Isrc_Vo_18V.png
VS= 1.8V RL= No Load
Figure 18. Output Swing vs. Sourcing Current, 1.8V
LPV811 LPV812 TG_Isrc_Vo_3p3.png
VS= 3.3V RL= No Load
Figure 20. Output Swing vs. Sourcing Current, 3.3V
LPV811 LPV812 TG_Isrc_Vo_5V.png
VS= 5V RL= No Load
Figure 22. Output Swing vs. Sourcing Current, 5V
LPV811 LPV812 TG_SSPULSE_1p8.png
TA = 25 RL= 10MΩ Vout = 200mVpp
VS= ±0.9V CL= 20pF AV = +1
Figure 24. Small Signal Pulse Response, 1.8V
LPV811 LPV812 TG_LSPULSE_1p8.png
TA = 25 RL= 10MΩ Vout = 1Vpp
VS= ±0.9V CL= 20pF AV = +1
Figure 26. Large Signal Pulse Response, 1.8V
LPV811 LPV812 802_CMRR_vs_Freq.png
TA = 25 RL= 10MΩ ΔVCM = 0.5Vpp
VS= 5V CL= 20p
VCM = Vs/2 AV = +1
Figure 28. CMRR vs Frequency
LPV811 LPV812 AVPH_5V_10M.png
TA = -40, 25, 125°C RL= 10MΩ VOUT = 200mVPP
VS= 5V CL= 20pF VCM = Vs/2
Figure 30. Open Loop Gain and Phase, 5V, 10 MΩ Load
LPV811 LPV812 AVPH_1p8V_1M.png
TA = -40, 25, 125°C RL= 1MΩ VOUT = 200mVPP
VS= 5V CL= 20pF VCM = Vs/2
Figure 32. Open Loop Gain and Phase, 5V, 1 MΩ Load
LPV811 LPV812 AVPH_5V_100k.png
TA = -40, 25, 125°C RL= 100kΩ VOUT = 200mVPP
VS= 5V CL= 20pF VCM = Vs/2
Figure 34. Open Loop Gain and Phase, 5V, 100kΩ Load
LPV811 LPV812 AVPH_1p8V_10M.png
TA = -40, 25, 125°C RL= 10MΩ VOUT = 200mVPP
VS= 1.8V CL= 20pF VCM = Vs/2
Figure 36. Open Loop Gain and Phase, 1.8V, 10 MΩ Load
LPV811 LPV812 AVPH_1p8V_1M.png
TA = -40, 25, 125°C RL= 1MΩ VOUT = 200mVPP
VS= 1.8V CL= 20pF VCM = Vs/2
Figure 38. Open Loop Gain and Phase, 1.8V, 1 MΩ Load
LPV811 LPV812 AVPH_1p8V_100k.png
A.
TA = -40, 25, 125°C RL= 100kΩ VOUT = 200mVPP
VS= 1.8V CL= 20pF VCM = Vs/2
Figure 40. Open Loop Gain and Phase, 1.8V, 100kΩ Load
LPV811 LPV812 811_Dist_3p3.png
VS = 3.3V LPV811
TA = 25°C VCM = V- RL=No Load
Figure 2. Offset Distribution of LPV811
LPV811 LPV812 812A_Dist_3p3.png
VS = 3.3V LPV812, Channel A
TA = 25°C VCM = V- RL=No Load
Figure 4. Offset Distribution of LPV812, CH A
LPV811 LPV812 812B_Dist_3p3.png
VS = 3.3V LPV812, Channel B
TA = 25°C VCM = V- RL=No Load
Figure 5. Offset Distribution of LPV812, CH B
LPV811 LPV812 TG_812_Iq_Vs_Vs.png
VCM = V- LPV812 RL=No Load
Figure 7. Supply Current vs. Supply Voltage, LPV812
LPV811 LPV812 TG_Vos_Vcm_3p3V.png
VS= 3.3V RL= 10MΩ
Figure 9. Typical Offset Voltage vs. Common Mode Voltage
LPV811 LPV812 Ib_vs_Temp.png
VS= 5V TA = -40 to 125 VCM = Vs/2
Figure 11. Input Bias Current vs. Temperature
LPV811 LPV812 IB_VCM_5V_m40.png
VS= 5V TA = -40°C
Figure 13. Input Bias Current vs. Common Mode Voltage
LPV811 LPV812 IB_VCM_5V_25C.png
VS= 5V TA = 25°C
Figure 15. Input Bias Current vs. Common Mode Voltage
LPV811 LPV812 IB_VCM_5V_125C.png
VS= 5V TA = 125°C
Figure 17. Input Bias Current vs. Common Mode Voltage
LPV811 LPV812 TG_Isnk_Vo_18V.png
VS= 1.8V RL= No Load
Figure 19. Output Swing vs. Sinking Current, 1.8V
LPV811 LPV812 TG_Isnk_Vo_3V.png
VS= 3.3V RL= No Load
Figure 21. Output Swing vs. Sinking Current, 3.3V
LPV811 LPV812 TG_Isnk_Vo_5V.png
VS= 5V RL= No Load
Figure 23. Output Swing vs. Sinking Current, 5V
LPV811 LPV812 TG_SSPULSE_5.png
TA = 25 RL= 10MΩ Vout = 200mVpp
VS= ±2.5V CL= 20pF AV = +1
Figure 25. Small Signal Pulse Response, 5V
LPV811 LPV812 TG_LSPULSE_5.png
TA = 25 RL= 10MΩ Vout = 2Vpp
VS= ±2.5V CL= 20pF AV = +1
Figure 27. Large Signal Pulse Response, 5V
LPV811 LPV812 PSRR_VS_FREQ.png
TA = 25 RL= 10MΩ ΔVS = 0.5Vpp
VS= 3.3V CL= 20p
VCM = Vs/2 AV = +1
Figure 29. ±PSRR vs Frequency
LPV811 LPV812 AVPH_3V_10M.png
TA = -40, 25, 125°C RL= 10MΩ VOUT = 200mVPP
VS= 3.3V CL= 20pF VCM = Vs/2
Figure 31. Open Loop Gain and Phase, 3.3V, 10 MΩ Load
LPV811 LPV812 AVPH_3V_1M.png
TA = -40, 25, 125°C RL= 1MΩ VOUT = 200mVPP
VS= 3.3V CL= 20pF VCM = Vs/2
Figure 33. Open Loop Gain and Phase, 3.3V, 1 MΩ Load
LPV811 LPV812 AVPH_3V_100k.png
TA = -40, 25, 125°C RL= 100kΩ VOUT = 200mVPP
VS= 3.3V CL= 20pF VCM = Vs/2
Figure 35. Open Loop Gain and Phase, 3.3V, 100kΩ Load
LPV811 LPV812 TG_Zout.png
TA = 25°C VS= 5 V RL= 10MΩ
Figure 37. Open Loop Output Impedance
LPV811 LPV812 Noise.png
TA = 25 RL= 1MΩ VCM = Vs/2
VS= 5V CL= 20pF AV = +1
Figure 39. Input Voltage Noise vs Frequency
LPV811 LPV812 EMIRR_3p3V.png
TA = 25 RL= 1MΩ VCM = Vs/2
VS= 3.3V CL= 20pF AV = +1
Figure 41. EMIRR Performance

7 Detailed Description

7.1 Overview

The LPV811 (single) and LPV812 (dual) series of nanoPower CMOS operational amplifiers are designed for long-life battery-powered and energy harvested applications. They operate on a single supply with operation as low as 1.6V. The Input Offset is trimmed to less than 300uV and the output is rail-to-rail and swings to within 3.5mV of the supplies with a 100kΩ load. The common-mode range extends to the negative supply making it ideal for single-supply applications. EMI protection has been employed internally to reduce the effects of EMI.

Parameters that vary significantly with operating voltages or temperature are shown in the Typical Characteristics curves.

7.2 Functional Block Diagram

LPV811 LPV812 Op_Amp_Triangle_Block_Diagram.gif

7.3 Feature Description

The amplifier's differential inputs consist of a non-inverting input (+IN) and an inverting input (–IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp VOUT is given by Equation 1:

Equation 1. VOUT = AOL (IN+ – IN–)

where

  • AOL is the open-loop gain of the amplifier, typically around 120 dB (1,000,000x, or 1,000,000 Volts per microvolt).

7.4 Device Functional Modes

7.4.1 Negative-Rail Sensing Input

The input common-mode voltage range of the LPV81x extends from (V-) to (V+) – 0.9 V. In this range, low offset can be expected with a minimum of 77dB CMRR. The LPV81x is protected from output "inversions" or "reversals".

7.4.2 Rail to Rail Output Stage

The LPV81x output voltage swings 3.5 mV from rails at 1.8 V supply, which provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages.

The LPV81x Maximum Output Voltage Swing graph defines the maximum swing possible under a particular output load.

7.4.3 Design Optimization for Nanopower Operation

When designing for ultra-low power, choose system feedback components carefully. To minimize quiescent current consumption, select large-value feedback resistors. Any large resistors will react with stray capacitance in the circuit and the input capacitance of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. A feedback capacitor may be required to assure stability and limit overshoot or gain peaking.

When possible, use AC coupling and AC feedback to reduce static current draw through the feedback elements. Use film or ceramic capacitors since large electrolytics may have large static leakage currents in the nanoamps.

7.4.4 Driving Capacitive Load

The LPV81x is internally compensated for stable unity gain operation, with a 8 kHz typical gain bandwidth. However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a capacitive load placed directly on the output of an amplifier along with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp might start oscillating.

In order to drive heavy (>50pF) capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 42. By using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. The recommended value for RISO is 30-50kΩ.

LPV811 LPV812 30054555.gif Figure 42. Resistive Isolation Of Capacitive Load

 
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