SDLS967H may   2016  – july 2023 LSF0108-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information (Q1)
    5. 6.5 Electrical Characteristics - RKS Package
    6. 6.6 Electrical Characteristics - PW Package
    7. 6.7 Switching Characteristics (Translating Down)
    8. 6.8 Switching Characteristics (Translating Up)
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Auto Bidirectional Voltage Translation
      2. 8.3.2 Output Enable
      3. 8.3.3 Wettable Flanks
    4. 8.4 Device Functional Modes
      1. 8.4.1 Up and Down Translation
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 I2C PMBus, SMBus, GPIO
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
          2. 9.2.1.1.2 Bias Circuitry
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Bidirectional Translation
          2. 9.2.1.2.2 Pull-Up Resistor Sizing
          3. 9.2.1.2.3 LSF0108-Q1 Bandwidth
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Mixed-Mode Voltage Translation
        1. 9.2.2.1 Single Supply Translation
        2. 9.2.2.2 Voltage Translation for Vref_B < Vref_A + 0.8 V
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.2 Voltage Translation for Vref_B < Vref_A + 0.8 V

As described in the Enable, Disable, and Reference Voltage Guidelines section, it is generally recommended that Vref_B > Vref_A + 0.8 V; however, the device can still operate in the condition where Vref_B < Vref_A + 0.8 V as long as additional considerations are made for the design.

Typical Operation (Vref_B > Vref_A + 0.8 V): in this scenario, pullup resistors are not required on the A-side for proper down-translation as is shown for channels 1 and 2 of Figure 9-6. The typical operating mode of the device is designed so that when down translating from B to A, the A-side I/O ports will clamp at Vref_A to provide proper voltage translation. For further explanation of device operation, see the Down Translation with the LSF Family video.

Requirements for Vref_B < Vref_A + 0.8 V Operation: in this scenario, there is not a large enough voltage difference between Vref_A and Vref_B to ensure that the A side I/O ports will be clamped at Vref_A, but rather at a voltage approximately equal to Vref_B – 0.8 V. For example, if Vref_B = 1.8 V and Vref_A = 1.2 V, the A-side I/Os will clamp to a voltage around 1.0 V. Therefore, to operate in such a condition, the following additional design considerations must be met:

  • Vref_B must be greater than VRef_A during operation (Vref_B > Vref_A)
  • Pullup resistors should be populated on A-side I/O ports so that the line will be fully pulled up to the desired voltage.

Figure 9-8 shows an example of this setup, where 1.2 V ↔ 1.8 V translation is achieved with the LSF0108-Q1. This type of setup also applies for other voltage nodes such as 1.8 V ↔ 2.5 V, 1.05 V ↔ 1.5 V, and others as long as the Recommended Operating Conditions table is followed.

GUID-20221012-SS0I-C2K8-CFGB-W8MCS1JRPK3M-low.svgFigure 9-8 1.2 V to 1.8 V Level Translation with LSF010x-Q1