SLVSCP5H July   2014  – April 2021 LSF0204 , LSF0204D

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
    7. 7.7  Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
    8. 7.8  Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
    9. 7.9  Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit AC Waveform for Outputs
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Support High Speed Translation, Greater than 100 MHz
      2. 9.3.2 Bidirectional Voltage Translation Without DIR Terminal
      3. 9.3.3 5-V Tolerance on IO Port and 125°C Support
      4. 9.3.4 Channel Specific Translation
      5. 9.3.5 Ioff, Partial Power Down Mode
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 I2C PMBus, SMBus, GPIO, Application
        1. 10.2.1.1 Design Requirements
          1. 10.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Bidirectional Translation
            1. 10.2.1.2.1.1 Pull-Up Resistor Sizing
          2. 10.2.1.2.2 LS Family Bandwidth
        3. 10.2.1.3 Application Curve
      2. 10.2.2 MDIO Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Multiple Voltage Translation in Single Device, Application
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGY|14
  • YZP|12
  • RUT|12
  • PW|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
VIKII = -18 mA, VEN = 0–1.2V
IIHVI = 5 V, VEN = 05.0µA
ICCBALeakage from Vref_B to Vref_AVref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND3.5µA
ICCA + ICCB(4)Total Current through GNDVref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or GND0.2µA
IINControl pin currentVref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0±1µA
IoffPower Off Leakage CurrentVref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND±1µA
CI(ref_A/B/EN)VI = 3 V or 07pF
Cio(off)VO = 3 V or 0, VEN = 05.06.0pF
Cio(on)VO = 3 V or 0, VEN = Vref_A10.513pF
(3)VIH (EN pin)High-level input voltageVref_A = 1.5 V to 4.5 V0.7×Vref_AV
VIL (EN pin)Low-level input voltageVref_A = 1.5 V to 4.5 V0.3×Vref_AV
VIH (EN pin)High-level input voltageVref_A= 1.0 V to 1.5 V0.8×Vref_AV
VIL (EN pin)Low-level input voltageVref_A = 1.0 V to 1.5 V0.3×Vref_AV
∆t/∆v (EN pin)Input transition rise or fall rate for EN pin10ns/V
ron (2)VI = 0, IO = 64 mAVref_A = VEN = 3.3 V; Vref_B = 5 V3Ω
Vref_A = VEN = 1.8 V; Vref_B = 5 V4
VI = 0, IO = 32 mAVref_A = VEN = 1.0 V; Vref_B = 5 V9Ω
Vref_A = VEN = 1.8 V; Vref_B = 5 V4
VI = 0, IO = 32 mA , Vref_A = VEN = 2.5 V; Vref_B = 5 V10Ω
VI = 1.8 V, IO = 15 mA, Vref_A = VEN = 3.3 V; Vref_B = 5 V5Ω
VI = 1.0 V, IO = 10 mA, Vref_A = VEN = 1.8 V; Vref_B = 3.3 V8Ω
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 3.3 V6Ω
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 1.8 V6Ω
(1) All typical values are at TA = 25°C.
(2) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
(3) Enable pin test conditions are for the LSF0204. The enable pin test conditions for LSF0204D are oppositely set.
(4) The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin