SNVSCJ1 August   2023 LV5144

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.3 Application Curves

GUID-D8D3ECB5-4141-45EF-AE46-E34CDF7CCAA2-low.gif
Figure 9-17 Efficiency vs IOUT and VIN
GUID-36585046-9D77-4BA0-B595-868B272B53E6-low.gif
VIN step to 48 V1.5-Ω Load
Figure 9-19 Start-Up, 8-A Resistive Load
GUID-DB70C033-31AF-4F19-AE80-E03943971715-low.gif
VIN = 48 V1.5-Ω Load
Figure 9-21 ENABLE ON, 10-A Resistive Load
GUID-FFBB8D41-85A6-4E4F-9250-1B4907028E7E-low.gif
VIN = 48 V
Figure 9-23 Load Transient Response, 1 A to 8 A to 1 A
GUID-7171C232-E8C9-4EC6-AB70-3108AC068F14-low.gif
VIN = 48 V
Figure 9-25 Load Transient Response, 4 A to 8 A to 4 A
GUID-17D856E8-556E-4012-93EA-8361103FC2AE-low.gif
IOUT = 4 A
Figure 9-27 Repetitive Line Transients, 24 V to 75 V
GUID-C9AD7AF5-BF31-4C33-AA14-156047A8F6F2-low.gif
VIN = 48 VFSW = 350 kHzIOUT = 8 A
Figure 9-29 SW Node and SYNCIN Voltages
GUID-37AD52E9-2EE7-419D-87F6-85C82B175995-low.gif
VIN = 48 VVOUT = 12 V6-A resistive load
Figure 9-31 CISPR 25 Class 5 Conducted EMI, 150 kHz to 30 MHz
GUID-1C5D6724-FF31-48F8-800F-FA804FB00ABB-low.gif
VIN = 48 VIOUT = 8 A
Figure 9-18 SW Node Voltages
GUID-7B6E3B81-6580-40C4-BF69-C09B9A57BF3E-low.gif
1.5-Ω Load
Figure 9-20 Shutdown By Input UVLO, 8-A Resistive Load
GUID-CD206205-4248-4511-A941-7CE8A4111319-low.gif
VIN = 48 V1.5-Ω Load
Figure 9-22 ENABLE OFF, 10-A Resistive Load
GUID-8B1C8303-5122-4BEC-8FEA-1B043AADFC75-low.gif
VIN = 48 V
Figure 9-24 Load Transient Response, 2 A to 8 A to 2 A
GUID-48644EAD-3414-46F9-84FB-27F727EC2B56-low.gif
VIN = 48 VIOUT = 8 A
Figure 9-26 Output Voltage Ripple
GUID-FA8B4B62-153E-4F1D-8A93-289B4D825A6E-low.gif
VIN = 48 VIOUT = 0 A
Figure 9-28 Pre-Biased Start-Up
GUID-DB74A499-CE6C-49C3-9199-3B9D819DFC2A-low.gif
VIN = 48 VIOUT = 8 A
Figure 9-30 SW Node and SYNCOUT Voltages
GUID-AE0E49CD-22EB-46FE-A484-28B86152B208-low.gif
VIN = 48 VVOUT = 12 V6-A resistive load
Figure 9-32 CISPR 25 Class 5 Conducted EMI, 30 MHz to 108 MHz