SNVSCJ1 August   2023 LV5144

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Pin Configuration and Functions
    1. 6.1 Wettable Flanks
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Range (VIN)
      2. 8.3.2  Output Voltage Setpoint and Accuracy (FB)
      3. 8.3.3  High-Voltage Bias Supply Regulator (VCC)
      4. 8.3.4  Precision Enable (EN/UVLO)
      5. 8.3.5  Power Good Monitor (PGOOD)
      6. 8.3.6  Switching Frequency (RT, SYNCIN)
        1. 8.3.6.1 Frequency Adjust
        2. 8.3.6.2 Clock Synchronization
      7. 8.3.7  Configurable Soft Start (SS/TRK)
        1. 8.3.7.1 Tracking
      8. 8.3.8  Voltage-Mode Control (COMP)
      9. 8.3.9  Gate Drivers (LO, HO)
      10. 8.3.10 Current Sensing and Overcurrent Protection (ILIM)
      11. 8.3.11 OCP Duty Cycle Limiter
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
      4. 8.4.4 Diode Emulation Mode
      5. 8.4.5 Thermal Shutdown
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Design and Implementation
      2. 9.1.2 Power Train Components
        1. 9.1.2.1 Inductor
        2. 9.1.2.2 Output Capacitors
        3. 9.1.2.3 Input Capacitors
        4. 9.1.2.4 Power MOSFETs
      3. 9.1.3 Control Loop Compensation
      4. 9.1.4 EMI Filter Design
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – 12-A High-Efficiency Synchronous Buck DC/DC Regulator
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Power Stage Layout
        2. 9.4.1.2 Gate Drive Layout
        3. 9.4.1.3 PWM Controller Layout
        4. 9.4.1.4 Thermal Design and Layout
        5. 9.4.1.5 Ground Plane Design
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
        1. 10.2.1.1 PCB Layout Resources
        2. 10.2.1.2 Thermal Design Resources
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated. VVIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Operating input voltage range 6 95 V
IQ-RUN Operating input current, not switching VEN/UVLO = 1.5 V, VSS/TRK = 0 V 2 mA
IQ-STBY Standby input current VEN/UVLO = 1 V 2 mA
IQ-SHDN Shutdown input current VEN/UVLO = 0 V, VVCC < 1 V 20 µA
VCC REGULATOR
VVCC VCC regulation voltage VSS/TRK = 0 V, 9 V < VVIN < 48 V, 0 mA < IVCC < 20 mA 7.5 V
VVCC-LDO VIN to VCC dropout voltage VVIN = 6 V, VSS/TRK = 0 V, IVCC = 20 mA 0.25 0.72 V
ISC-LDO VCC short-circuit current VSS/TRK = 0 V, VVCC = 0 V 40 50 70 mA
VVCC-UV VCC undervoltage threshold VCC rising 4.8 4.93 5.2 V
VVCC-UVH VCC undervoltage hysteresis Rising threshold – falling threshold 0.26 V
VVCC-EXT Minimum external bias voltage Voltage required to disable VCC regulator 8 V
IVCC External VCC input current, not switching VSS/TRK = 0 V, VVCC = 13 V 2.3 mA
ENABLE AND INPUT UVLO
VSHDN Shutdown to standby threshold VEN/UVLO rising 0.42 V
VSHDN-HYS Shutdown threshold hysteresis EN/UVLO Rising threshold – falling threshold 50 mV
VEN Standby to operating threshold VEN/UVLO rising 1.164 1.2 1.236 V
IEN-HYS Standby to operating hysteresis current VEN/UVLO = 1.5 V 9 10 11 µA
ERROR AMPLIFIER
VREF FB reference Voltage FB connected to COMP 792 800 808 mV
IFB-BIAS FB input bias current VFB = 0.8 V, -40℃ to +125℃ –100 100 nA
IFB-BIAS FB input bias current VFB =0.8 V, TJ = +150℃ –200 200 nA
VCOMP-OH
 		 COMP output high voltage VFB = 0 V, COMP sourcing 1 mA 5 V
VCOMP-OL COMP output low voltage COMP sinking 1 mA 0.3 V
AVOL DC gain 94 dB
GBW Unity gain bandwidth 6.5 MHz
SOFT-STARTand VOLTAGE TRACKING
ISS SS/TRK capacitor charging current VSS/TRK = 0 V 8.5 10 12 µA
RSS SS/TRK discharge FET resistance VEN/UVLO = 1 V, VSS/TRK = 0.1 V 11 Ω
VSS-FB SS/TRK to FB offset VSS/TRK – VFB, VFB = 0.8 V –15 0 15 mV
VSS-CLAMP SS/TRK clamp voltage VFB = 0.8 V 0.115 V
POWER GOOD INDICATOR
PGUTH FB upper threshold for PGOOD high to low % of VREF, VFB rising 108 %
PGLTH FB lower threshold for PGOOD high to low % of VREF, VFB falling 92 %
PGHYS_U PGOOD upper theshold hysteresis % of VREF 3 %
PGHYS_L PGOOD lower threshold hysteresis % of VREF 2 %
TPG-RISE PGOOD rising filter FB to PGOOD rising edge 25 us
TPG-FALL PGOOD falling filter FB to PGOOD falling edge 25 us
VPG-OL PGOOD low state output voltage VFB = 0.9 V, IPGOOD = 2 mA 150 mV
IPG-OH PGOOD high state leakage current VFB = 0.8 V, VPGOOD = 13 V, -40℃ to +150℃ 400 nA
IPG-OH PGOOD high state leakage current VFB = 0.8 V, VPGOOD = 13 V 400 nA
OSCILLATOR
FSW1 Oscilator frequency – 1 RRT = 100 kΩ 100 kHz
FSW2 Oscillator frequency – 2 RRT = 25 kΩ 400 kHz
FSW3 Oscillator frequency – 3 RRT = 12.5 kΩ 780 kHz
SYNCHRONIZATION INPUT AND OUTPUT
FSYNC SYNCIN external clock frequency range % of nominal frequency set by RRT –20 50 %
VSYNC-IH SYNCIN input logic high 2 V
VSYNC-IL SYNCIN input logic low 0.8 V
RSYNC-IN SYNCIN input resistance VSYNCIN = 3 V 20 kΩ
TSYNCI-PW SYNCIN input minimum pulsewidth Minimum high state or low state duration 50 ns
VSYNCO-OH SYNCOUT high-state output voltage ISYNCOUT = –1 mA (sourcing current) 3 V
VSYNCO-OL SYNCOUT low-state output voltage ISYNCOUT = 1 mA (sinking current) 0.4 V
TSYNCOUT Delay from HO rising to SYNCOUT leading edge VSYNCIN = 0 V, TS = 1/FSW, FSW set by RRT TS/2 – 140 ns
TSYNCIN Delay from SYNCIN rising to HO leading edge 50% to 50% 150 ns
GATE DRIVERS
RHO-UP HO high state resistance, HO to BST VBST – VSW = 7 V, IHO = –100 mA 1.5 Ω
RHO-DOWN HO low state resistance, HO to SW VBST – VSW = 7 V, IHO = 100 mA 0.9 Ω
RLO-UP LO high state resistance, LO to VCC VBST – VSW = 7 V, ILO = –100 mA 1.5 Ω
RLO-DOWN LO low state resistance, LO to PGND VBST – VSW = 7 V, ILO = 100 mA 0.9 Ω
IHOH, ILOH HO, LO source current VBST – VSW = 7 V, HO = SW, LO = AGND 2.3 A
IHOL, ILOL HO, LO sink current VBST – VSW = 7 V, HO = BST, LO = VCC 3.5 A
THO-TR, TLO-TR HO, LO rise times VBST – VSW = 7 V, CLOAD = 1 nF, 20% to 80% 7 ns
THO-TF, TLO-TF HO, LO fall times VBST – VSW = 7 V, CLOAD = 1 nF, 80% to 20% 4 ns
THO-DT HO turn-on deadtime VBST – VSW = 7 V, 50% to 50% 14 ns
TLO-DT LO turn-on deadtime VBST – VSW = 7 V, 50% to 50% 14 ns
BOOTSTRAP DIODE AND UNDER-VOLTAGE THRESHOLD
VBST-FWD VCC to BST VCC to BST, BST pin sourcing 20 mA 0.75 0.9 V
IQ-BST BST to SW quiescent current, not switching VSS/TRK = 0 V, VSW = 48 V, VBST = 54 V 80 µA
VBST-UV BST to SW undervoltage detection VBST – VSW falling 3.4 V
VBST-HYS BST to SW undervoltage hysteresis VBST – VSW rising 0.42 V
PWM CONTROL
TON(min) Minimum controllable on-time VBST – VSW = 7 V, HO 50% to 50% 45 ns
TOFF(min) Minimum off-time VBST – VSW = 7 V, HO 50% to 50% 145 ns
DC100KHz Maximum duty cycle FSW = 100 kHz, 5.5 V < VVIN < 60 V 98 99 %
DC400kHz FSW = 400 kHz, 5.5 V < VVIN < 60 V 90 94 %
VRAMP(min) RAMP valley voltage (COMP at 0% duty cycle) 300 mV
kFF PWM feedforward gain (VIN / VRAMP) 5.5 V < VVIN < 100 V 15 V / V
OVER CURRENT PROTECT (OCP) - VALLEY CURRENT LIMITING
IRS ILIM source current, RSENSE Mode Low voltage detected at ILIM 100 µA
IRDSON ILIM source current, RDS-ON mode SW voltage detected at ILIM , TJ = 25°C 180 200 220 µA
IRSTC ILIM current tempco RDS-ON mode 4500 ppm/°C
IRDSONTC ILIM current tempco RSENSE mode 0 ppm/°C
VILIM-TH ILIM comparator threshold at ILIM –8 –2 3.5 mV
SHORT CIRCUIT PROTECTION (SCP) - DUTY CYCLE CLAMP
VCLAMP-OS Clamp offset voltage - No current limiting COMP to duty cycle clamp voltage 0.2 + VVIN/75 V
VCLAMP-MIN Minimum duty cycle clamp voltage Clamp voltage with continuous OCP 0.3 + VVIN/150 V
HICCUP MODE FAULT PROTECTION
CHICC-DEL Hiccup mode activation delay Clock cycles with current limiting before off-time activated 128 cycles
CHICCUP Hiccup mode off time after activation Clock cycles with no switching followed by SS/TRK release 8192 cycles
DIODE EMULATION / DCM OPERATION
VZCD-SS Zero-cross detect (ZCD) soft-start ramp ZCD threshold measured at SW pin 50 cycles after first HO pulse 0 mV
VZCD-DIS Zero-cross detect disable threshold ZCD threshold measured at SW pin 1000 cycles after first HO pulse 200 mV
VDEM-TH Diode emulation zero-cross threshold Measured at SW with VSW rising 0 mV
THERMAL SHUTDOWN
TSD Thermal shutdown threshold TJ rising 175 °C
TSD-HYS Thermal shutdown hysteresis 20 °C
Switching Characteristics
THO-TR, TLO-TR HO, LO rise times VBST-VSW =7 V, CLOAD =1 nF, 20% to 80%          7               ns
THO-TF, TLO-TF HO, fall times VBST -VSW =7 V, CLOAD =1 nF, 20% to 80%          4                ns
THO-DT HO turnon dead time VBST - VSW =7 V, LO off to HO on, 50% to 50%         14                 ns