SLLS576G July 2003 – February 2024 MAX202
PRODUCTION DATA
The HBM of ESD testing is shown in Figure 7-2. Figure 7-3 shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of concern, and subsequently discharged into the device under test (DUT) through a 1.5-kΩ resistor.