SLLSFU1A December 2023 – July 2024 MCF8315C
PRODMIX
If at any time input supply voltage on the VM pins rises higher than VOVP, all the integrated FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and OVP bits are set to 1b in the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit. Setting the OVP_EN to 0b disables this protection feature.
The OVP threshold can be set to 22-V or 34-V based on the OVP_SEL bit.