SLLSFU1 Data sheet

SLLSFU1A December 2023 – July 2024 MCF8315C

PRODMIX

Package Options

Mechanical Data (Package|Pins)

PWP|24
- MPDS372A
RRY|32
- MPQF713A

Thermal pad, mechanical data (Package|Pins)

PWP|24
- PPTD395
RRY|32
- QFND764

Orderable Information

5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
Standard-mode
f_SCL	SCL clock frequency		0	100	kHz
t_{HD_STA}	Hold time (repeated) START condition	After this period, the first clock pulse is generated	4		µs
t_LOW	LOW period of the SCL clock		4.7		µs
t_HIGH	HIGH period of the SCL clock		4		µs
t_{SU_STA}	Set-up time for a repeated START condition		4.7		µs
t_{HD_DAT}	Data hold time ⁽²⁾	I2C bus devices	0 ⁽³⁾	⁽⁴⁾	µs
t_{SU_DAT}	Data set-up time		250		ns
t_r	Rise time for both SDA and SCL signals			1000	ns
t_f	Fall time of both SDA and SCL signals ⁽³⁾⁽⁶⁾⁽⁷⁾⁽⁸⁾			300	ns
t_{SU_STO}	Set-up time for STOP condition		4		µs
t_BUF	Bus free time between STOP and START condition		4.7		µs
C_b	Capacitive load for each bus line ⁽⁹⁾			400	pF
t_{VD_DAT}	Data valid time ⁽¹⁰⁾			3.45 ⁽⁴⁾	µs
t_{VD_ACK}	Data valid acknowledge time ⁽¹¹⁾			3.45 ⁽⁴⁾	µs
V_nL	Noise margin at the LOW level	For each connected device (including hysteresis)	0.1*AVDD		V
V_nh	Noise margin at the HIGHlevel	For each connected device (including hysteresis)	0.2*AVDD		V
Fast-mode
f_SCL	SCL clock frequency		0	400	KHz
t_{HD_STA}	Hold time (repeated) START condition	After this period, the first clock pulse is generated	0.6		µs
t_LOW	LOW period of the SCL clock		1.3		µs
t_HIGH	HIGH period of the SCL clock		0.6		µs
t_{SU_STA}	Set-up time for a repeated START condition		0.6		µs
t_{HD_DAT}	Data hold time ⁽²⁾		0 ⁽³⁾	⁽⁴⁾	µs
t_{SU_DAT}	Data set-up time		100 ⁽⁵⁾		ns
t_r	Rise time for both SDA and SCL signals		20	300	ns
t_f	Fall time of both SDA and SCL signals ⁽³⁾⁽⁶⁾⁽⁷⁾⁽⁸⁾		20 x (AVDD/5.5V)	300	ns
t_{SU_STO}	Set-up time for STOP condition		0.6		µs
t_BUF	Bus free time between STOP and START condition		1.3		µs
C_b	Capacitive load for each bus line ⁽⁹⁾			400	pF
t_{VD_DAT}	Data valid time ⁽¹⁰⁾			0.9 ⁽⁴⁾	µs
t_{VD_ACK}	Data valid acknowledge time ⁽¹¹⁾			0.9 ⁽⁴⁾	µs
V_nL	Noise margin at the LOW level	For each connected device (including hysteresis)	0.1*AVDD		V
V_nh	Noise margin at the HIGHlevel	For each connected device (including hysteresis)	0.2*AVDD		V

(2) t_{HD_DAT} is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V_IH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.

(4) The maximum t_{HD_DAT} could be 3.45 µs and .9 µs for Standard-mode and Fast-mode, but must be less than the maximum of t_{VD_DAT} or t_{VD_ACK} by a transition time. This maximum must only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal. If the clock stretched the SCL, the data must be valid by the set-up time before it releases the clock.

(5) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement t_{SU_DAT} 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_r(max) + t_{SU_DAT} = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.

(6) If mixed with HS-mode devices, faster fall times according to Table 10 are allowed.

(7) The maximum t_f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t_f is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t_f.

(8) In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing.

(9) The maximum bus capacitance allowable may vary from the value depending on the actual operating voltage and frequency of the application.

(10) t_{VD_DAT} = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

(11) t_{VD_ACK} = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, dependging on which one is worse).