SLLSFV2 August   2023 MCF8316C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Reference Profiles
          2. 7.3.8.5.2 Staircase Speed Profile
          3. 7.3.8.5.3 Forward-Reverse Speed Profile
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Torque Mode
        5. 7.3.11.5 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Active Braking
      16. 7.3.16 Output PWM Switching Frequency
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Low-Side Braking
        3. 7.3.19.3 High-Side Braking
        4. 7.3.19.4 Active Spin-Down
        5. 7.3.19.5 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG during Open and Closed Loop States
        3. 7.3.20.3 FG during Fault and Idle States
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.22.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.22.10 FET Thermal Warning (OTW)
        11. 7.3.22.11 FET Thermal Shutdown (TSD_FET)
        12. 7.3.22.12 Motor Lock (MTR_LCK)
          1. 7.3.22.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.22.13 Motor Lock Detection
          1. 7.3.22.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.13.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.22.14 MPET Faults
        15. 7.3.22.15 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Anti voltage surge (AVS)
        6. 8.2.1.6 Real time variable tracking using DACOUT
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8.5 Algorithm_Variables Registers

Table 7-63 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not listed in Table 7-63 should be considered as reserved locations and the register contents should not be modified.

Table 7-63 ALGORITHM_VARIABLES Registers
Offset Acronym Register Name Section
190h ALGORITHM_STATE Current Algorithm State Register Go
196h FG_SPEED_FDBK FG Speed Feedback Register Go
410h BUS_CURRENT Calculated DC Bus Current Register Go
440h PHASE_CURRENT_A Measured Current on Phase A Register Go
442h PHASE_CURRENT_B Measured Current on Phase B Register Go
444h PHASE_CURRENT_C Measured Current on Phase C Register Go
468h CSA_GAIN_FEEDBACK CSA Gain Register Go
472h VOLTAGE_GAIN_FEEDBACK Voltage Gain Register Go
476h VM_VOLTAGE VM Voltage Register Go
47Ah PHASE_VOLTAGE_VA Phase A Voltage Register Go
47Ch PHASE_VOLTAGE_VB Phase B Voltage Register Go
47Eh PHASE_VOLTAGE_VC Phase C Voltage Register Go
4B6h SIN_COMMUTATION_ANGLE Sine of Commutation Angle Go
4B8h COS_COMMUTATION_ANGLE Cosine of Commutation Angle Go
4D2h IALPHA IALPHA Current Register Go
4D4h IBETA IBETA Current Register Go
4D6h VALPHA VALPHA Voltage Register Go
4D8h VBETA VBETA Voltage Register Go
4E2h ID Measured d-axis Current Register Go
4E4h IQ Measured q-axis Current Register Go
4E6h VD VD Voltage Register Go
4E8h VQ VQ Voltage Register Go
524h IQ_REF_ROTOR_ALIGN Align Current Reference Go
53Ch SPEED_REF_OPEN_LOOP Open Loop Speed Register Go
54Ch IQ_REF_OPEN_LOOP Open Loop Current Reference Go
5D4h SPEED_REF_CLOSED_LOOP Speed Reference Register Go
606h ID_REF_CLOSED_LOOP Reference for Current Loop Register Go
608h IQ_REF_CLOSED_LOOP Reference for Current Loop Register Go
682h ISD_STATE ISD State Register Go
68Ch ISD_SPEED ISD Speed Register Go
6C0h IPD_STATE IPD State Register Go
704h IPD_ANGLE Calculated IPD Angle Register Go
74Ah ED Estimated BEMF EQ Register Go
74Ch EQ Estimated BEMF ED Register Go
75Ah SPEED_FDBK Speed Feedback Register Go
75Eh THETA_EST Estimated rotor Position Register Go

Complex bit access types are encoded to fit into small table cells. Table 7-64 shows the codes that are used for access types in this section.

Table 7-64 Algorithm_Variables Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

7.8.5.1 ALGORITHM_STATE Register (Offset = 190h) [Reset = 0000h]

ALGORITHM_STATE is shown in Figure 7-89 and described in Table 7-65.

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Current Algorithm State Register

Figure 7-89 ALGORITHM_STATE Register
15141312111098
ALGORITHM_STATE
R-0h
76543210
ALGORITHM_STATE
R-0h
Table 7-65 ALGORITHM_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ALGORITHM_STATER0h 16-bit value indicating current state of device
0h = MOTOR_IDLE
1h = MOTOR_ISD
2h = MOTOR_TRISTATE
3h = MOTOR_BRAKE_ON_START
4h = MOTOR_IPD
5h = MOTOR_SLOW_FIRST_CYCLE
6h = MOTOR_ALIGN
7h = MOTOR_OPEN_LOOP
8h = MOTOR_CLOSED_LOOP_UNALIGNED
9h = MOTOR_CLOSED_LOOP_ALIGNED
Ah = MOTOR_CLOSED_LOOP_ACTIVE_BRAKING
Bh = MOTOR_SOFT_STOP
Ch = MOTOR_RECIRCULATE_STOP
Dh = MOTOR_BRAKE_ON_STOP
Eh = MOTOR_FAULT
Fh = MOTOR_MPET_MOTOR_STOP_CHECK
10h = MOTOR_MPET_MOTOR_STOP_WAIT
11h = MOTOR_MPET_MOTOR_BRAKE
12h = MOTOR_MPET_ALGORITHM_PARAMETERS_INIT
13h = MOTOR_MPET_RL_MEASURE
14h = MOTOR_MPET_KE_MEASURE
15h = MOTOR_MPET_STALL_CURRENT_MEASURE
16h = MOTOR_MPET_TORQUE_MODE
17h = MOTOR_MPET_DONE
18h = MOTOR_MPET_FAULT

7.8.5.2 FG_SPEED_FDBK Register (Offset = 196h) [Reset = 00000000h]

FG_SPEED_FDBK is shown in Figure 7-90 and described in Table 7-66.

Return to the Summary Table.

Speed Feedback from FG

Figure 7-90 FG_SPEED_FDBK Register
313029282726252423222120191817161514131211109876543210
FG_SPEED_FDBK
R-0h
Table 7-66 FG_SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0FG_SPEED_FDBKR0h 32-bit unsigned value indicating absolute estimated rotor speed estimatedSpeed = (FG_SPEED_FDBK / 227)*MAXIMUM_SPEED_HZ

7.8.5.3 BUS_CURRENT Register (Offset = 410h) [Reset = 00000000h]

BUS_CURRENT is shown in Figure 7-91 and described in Table 7-67.

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Calculated Supply Current Register

Figure 7-91 BUS_CURRENT Register
313029282726252423222120191817161514131211109876543210
BUS_CURRENT
R-0h
Table 7-67 BUS_CURRENT Register Field Descriptions
BitFieldTypeResetDescription
31-0BUS_CURRENTR0h 32-bit signed value indicating bus current. Negative value is represented in two's complement iBus = (BUS_CURRENT / 227) * Base_Current/8

7.8.5.4 PHASE_CURRENT_A Register (Offset = 440h) [Reset = 00000000h]

PHASE_CURRENT_A is shown in Figure 7-92 and described in Table 7-68.

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Measured current on Phase A Register

Figure 7-92 PHASE_CURRENT_A Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_A
R-0h
Table 7-68 PHASE_CURRENT_A Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_AR0h 32-bit signed value indicating measured current on Phase A. Negative value is represented in two's complement iA = (PHASE_CURRENT_A / 227) * Base_Current/8

7.8.5.5 PHASE_CURRENT_B Register (Offset = 442h) [Reset = 00000000h]

PHASE_CURRENT_B is shown in Figure 7-93 and described in Table 7-69.

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Measured current on Phase B Register

Figure 7-93 PHASE_CURRENT_B Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_B
R-0h
Table 7-69 PHASE_CURRENT_B Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_BR0h 32-bit signed value indicating measured current on Phase B. Negative value is represented in two's complement iB = (PHASE_CURRENT_B / 227) * Base_Current/8

7.8.5.6 PHASE_CURRENT_C Register (Offset = 444h) [Reset = 00000000h]

PHASE_CURRENT_C is shown in Figure 7-94 and described in Table 7-70.

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Measured current on Phase C Register

Figure 7-94 PHASE_CURRENT_C Register
313029282726252423222120191817161514131211109876543210
PHASE_CURRENT_C
R-0h
Table 7-70 PHASE_CURRENT_C Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_CR0h 32-bit signed value indicating measured current on Phase C. Negative value is represented in two's complement iC = (PHASE_CURRENT_C / 227) * Base_Current/8

7.8.5.7 CSA_GAIN_FEEDBACK Register (Offset = 468h) [Reset = 0000h]

CSA_GAIN_FEEDBACK is shown in Figure 7-95 and described in Table 7-71.

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VM Voltage Register

Figure 7-95 CSA_GAIN_FEEDBACK Register
15141312111098
CSA_GAIN_FEEDBACK
R-0h
76543210
CSA_GAIN_FEEDBACK
R-0h
Table 7-71 CSA_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0CSA_GAIN_FEEDBACKR0h 16-bit value indicating current sense gain
0h = MAX_CSA_GAIN * 8
1h = MAX_CSA_GAIN * 4
2h = MAX_CSA_GAIN * 2
3h = MAX_CSA_GAIN * 1

7.8.5.8 VOLTAGE_GAIN_FEEDBACK Register (Offset = 472h) [Reset = 0000h]

VOLTAGE_GAIN_FEEDBACK is shown in Figure 7-96 and described in Table 7-72.

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Voltage Gain Register

Figure 7-96 VOLTAGE_GAIN_FEEDBACK Register
15141312111098
VOLTAGE_GAIN_FEEDBACK
R-0h
76543210
VOLTAGE_GAIN_FEEDBACK
R-0h
Table 7-72 VOLTAGE_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0VOLTAGE_GAIN_FEEDBACKR0h 16-bit value indicating voltage gain
0h = 60V
1h = 30V
2h = 15V

7.8.5.9 VM_VOLTAGE Register (Offset = 476h) [Reset = 00000000h]

VM_VOLTAGE is shown in Figure 7-97 and described in Table 7-73.

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Supply voltage register

Figure 7-97 VM_VOLTAGE Register
313029282726252423222120191817161514131211109876543210
VM_VOLTAGE
R-0h
Table 7-73 VM_VOLTAGE Register Field Descriptions
BitFieldTypeResetDescription
31-0VM_VOLTAGER0h 32-bit value indicating dc bus voltage DC Bus Voltage = VM_VOLTAGE * 60 / 227

7.8.5.10 PHASE_VOLTAGE_VA Register (Offset = 47Ah) [Reset = 00000000h]

PHASE_VOLTAGE_VA is shown in Figure 7-98 and described in Table 7-74.

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Phase A Voltage Register

Figure 7-98 PHASE_VOLTAGE_VA Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VA
R-0h
Table 7-74 PHASE_VOLTAGE_VA Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VAR0h 32-bit value indicating Phase Voltage Va during ISD Phase A voltage = PHASE_VOLTAGE_VA * 60 / (sqrt(3) * 227)

7.8.5.11 PHASE_VOLTAGE_VB Register (Offset = 47Ch) [Reset = 00000000h]

PHASE_VOLTAGE_VB is shown in Figure 7-99 and described in Table 7-75.

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Phase B Voltage Register

Figure 7-99 PHASE_VOLTAGE_VB Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VB
R-0h
Table 7-75 PHASE_VOLTAGE_VB Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VBR0h 32-bit value indicating Phase Voltage Vb during ISD Phase B voltage = PHASE_VOLTAGE_VB * 60 / (sqrt(3) * 227)

7.8.5.12 PHASE_VOLTAGE_VC Register (Offset = 47Eh) [Reset = 00000000h]

PHASE_VOLTAGE_VC is shown in Figure 7-100 and described in Table 7-76.

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Phase C Voltage Register

Figure 7-100 PHASE_VOLTAGE_VC Register
313029282726252423222120191817161514131211109876543210
PHASE_VOLTAGE_VC
R-0h
Table 7-76 PHASE_VOLTAGE_VC Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VCR0h 32-bit value indicating Phase Voltage Vc during ISD Phase C voltage = PHASE_VOLTAGE_VC * 60 / (sqrt(3) * 227)

7.8.5.13 SIN_COMMUTATION_ANGLE Register (Offset = 4B6h) [Reset = 00000000h]

SIN_COMMUTATION_ANGLE is shown in Figure 7-101 and described in Table 7-77.

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Sine of Commutation Angle

Figure 7-101 SIN_COMMUTATION_ANGLE Register
313029282726252423222120191817161514131211109876543210
SIN_COMMUTATION_ANGLE
R-0h
Table 7-77 SIN_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0SIN_COMMUTATION_ANGLER0h 32-bit signed value indicating sine of commutation Angle. Negative value is represented in two's complement sinCommutationAngle = (SIN_COMMUTATION_ANGLE / 227)

7.8.5.14 COS_COMMUTATION_ANGLE Register (Offset = 4B8h) [Reset = 00000000h]

COS_COMMUTATION_ANGLE is shown in Figure 7-102 and described in Table 7-78.

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Cosine of Commutation Angle

Figure 7-102 COS_COMMUTATION_ANGLE Register
313029282726252423222120191817161514131211109876543210
COS_COMMUTATION_ANGLE
R-0h
Table 7-78 COS_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0COS_COMMUTATION_ANGLER0h 32-bit signed value indicating cosine of commutation Angle. Negative value is represented in two's complement cosCommutationAngle = (COS_COMMUTATION_ANGLE / 227)

7.8.5.15 IALPHA Register (Offset = 4D2h) [Reset = 00000000h]

IALPHA is shown in Figure 7-103 and described in Table 7-79.

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IALPHA Current Register

Figure 7-103 IALPHA Register
313029282726252423222120191817161514131211109876543210
IALPHA
R-0h
Table 7-79 IALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0IALPHAR0h 32-bit signed value indicating calculated IALPHA. Negative value is represented in two's complement iAlpha = (IALPHA / 227) * Base_Current/8

7.8.5.16 IBETA Register (Offset = 4D4h) [Reset = 00000000h]

IBETA is shown in Figure 7-104 and described in Table 7-80.

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IBETA Current Register

Figure 7-104 IBETA Register
313029282726252423222120191817161514131211109876543210
IBETA
R-0h
Table 7-80 IBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0IBETAR0h 32-bit signed value indicating calculated IBETA. Negative value is represented in two's complement iBeta = (IBETA / 227) * Base_Current/8

7.8.5.17 VALPHA Register (Offset = 4D6h) [Reset = 00000000h]

VALPHA is shown in Figure 7-105 and described in Table 7-81.

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VALPHA Voltage Register

Figure 7-105 VALPHA Register
313029282726252423222120191817161514131211109876543210
VALPHA
R-0h
Table 7-81 VALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALPHAR0h 32-bit signed value indicating calculated VALPHA. Negative value is represented in two's complement vAlpha = (VALPHA / 227) * 60 / sqrt(3)

7.8.5.18 VBETA Register (Offset = 4D8h) [Reset = 00000000h]

VBETA is shown in Figure 7-106 and described in Table 7-82.

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VBETA Voltage Register

Figure 7-106 VBETA Register
313029282726252423222120191817161514131211109876543210
VBETA
R-0h
Table 7-82 VBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0VBETAR0h 32-bit signed value indicating calculated VBETA. Negative value is represented in two's complement vBeta = (VBETA / 227) * 60 / sqrt(3)

7.8.5.19 ID Register (Offset = 4E2h) [Reset = 00000000h]

ID is shown in Figure 7-107 and described in Table 7-83.

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Measured d-axis Current Register

Figure 7-107 ID Register
313029282726252423222120191817161514131211109876543210
ID
R-0h
Table 7-83 ID Register Field Descriptions
BitFieldTypeResetDescription
31-0IDR0h 32-bit signed value indicating estimated Id. Negative value is represented in two's complement id = (ID / 227) * Base_Current/8

7.8.5.20 IQ Register (Offset = 4E4h) [Reset = 00000000h]

IQ is shown in Figure 7-108 and described in Table 7-84.

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Measured q-axis Current Register

Figure 7-108 IQ Register
313029282726252423222120191817161514131211109876543210
IQ
R-0h
Table 7-84 IQ Register Field Descriptions
BitFieldTypeResetDescription
31-0IQR0h 32-bit signed value indicating estimated Iq. Negative value is represented in two's complement iq = (IQ / 227) * Base_Current/8

7.8.5.21 VD Register (Offset = 4E6h) [Reset = 00000000h]

VD is shown in Figure 7-109 and described in Table 7-85.

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VD Voltage Register

Figure 7-109 VD Register
313029282726252423222120191817161514131211109876543210
VD
R-0h
Table 7-85 VD Register Field Descriptions
BitFieldTypeResetDescription
31-0VDR0h 32-bit signed value indicating applied Vd. Negative value is represented in two's complement vd = (VD / 227) * 60 / sqrt(3)

7.8.5.22 VQ Register (Offset = 4E8h) [Reset = 00000000h]

VQ is shown in Figure 7-110 and described in Table 7-86.

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VQ Voltage Register

Figure 7-110 VQ Register
313029282726252423222120191817161514131211109876543210
VQ
R-0h
Table 7-86 VQ Register Field Descriptions
BitFieldTypeResetDescription
31-0VQR0h 32-bit signed value indicating applied Vq. Negative value is represented in two's complement vq = (VQ / 227) * 60 / sqrt(3)

7.8.5.23 IQ_REF_ROTOR_ALIGN Register (Offset = 524h) [Reset = 00000000h]

IQ_REF_ROTOR_ALIGN is shown in Figure 7-111 and described in Table 7-87.

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Align Current Reference

Figure 7-111 IQ_REF_ROTOR_ALIGN Register
313029282726252423222120191817161514131211109876543210
IQ_REF_ROTOR_ALIGN
R-0h
Table 7-87 IQ_REF_ROTOR_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_ROTOR_ALIGNR0h 32-bit signed value indicating Align Current Reference. Negative value is represented in two's complement iqRefRotorAlign = (IQ_REF_ROTOR_ALIGN / 227) * Base_Current/8

7.8.5.24 SPEED_REF_OPEN_LOOP Register (Offset = 53Ch) [Reset = 00000000h]

SPEED_REF_OPEN_LOOP is shown in Figure 7-112 and described in Table 7-88.

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Speed at which motor transitions to close loop

Figure 7-112 SPEED_REF_OPEN_LOOP Register
313029282726252423222120191817161514131211109876543210
SPEED_REF_OPEN_LOOP
R-0h
Table 7-88 SPEED_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_OPEN_LOOPR0h 32-bit signed value indicating Open Loop Speed. The value is positive for OUTA-OUTB-OUTC and Negative and represented in two's complement for OUTA-OUTC-OUTB openLoopSpeedRef = (SPEED_REF_OPEN_LOOP / 227) * MAX_SPEED (Hz)

7.8.5.25 IQ_REF_OPEN_LOOP Register (Offset = 54Ch) [Reset = 00000000h]

IQ_REF_OPEN_LOOP is shown in Figure 7-113 and described in Table 7-89.

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Open Loop Current Reference

Figure 7-113 IQ_REF_OPEN_LOOP Register
313029282726252423222120191817161514131211109876543210
IQ_REF_OPEN_LOOP
R-0h
Table 7-89 IQ_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_OPEN_LOOPR0h 32-bit signed value indicating Open Loop Current Reference. Negative value is represented in two's complement iqRefOpenLoop = (IQ_REF_OPEN_LOOP / 227) * Base_Current/8

7.8.5.26 SPEED_REF_CLOSED_LOOP Register (Offset = 5D4h) [Reset = 00000000h]

SPEED_REF_CLOSED_LOOP is shown in Figure 7-114 and described in Table 7-90.

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Speed Reference Register

Figure 7-114 SPEED_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
SPEED_REF_CLOSED_LOOP
R-0h
Table 7-90 SPEED_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_CLOSED_LOOPR0h 32-bit signed value indicating reference for speed loop. The value is positive for OUTA-OUTB-OUTC and Negative and represented in two's complement for OUTA-OUTC-OUTB Speed Reference in closed loop (Hz) = (SPEED_REF_CLOSED_LOOP/ 227) * MAX_SPEED (Hz)

7.8.5.27 ID_REF_CLOSED_LOOP Register (Offset = 606h) [Reset = 00000000h]

ID_REF_CLOSED_LOOP is shown in Figure 7-115 and described in Table 7-91.

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Reference for Current Loop Register

Figure 7-115 ID_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
ID_REF_CLOSED_LOOP
R-0h
Table 7-91 ID_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_REF_CLOSED_LOOPR0h 32-bit signed value indicating Id_ref for flux loop. Negative value is represented in two's complement idRefClosedLoop = (ID_REF_CLOSED_LOOP / 227) * Base_Current/8

7.8.5.28 IQ_REF_CLOSED_LOOP Register (Offset = 608h) [Reset = 00000000h]

IQ_REF_CLOSED_LOOP is shown in Figure 7-116 and described in Table 7-92.

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Reference for Current Loop Register

Figure 7-116 IQ_REF_CLOSED_LOOP Register
313029282726252423222120191817161514131211109876543210
IQ_REF_CLOSED_LOOP
R-0h
Table 7-92 IQ_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_CLOSED_LOOPR0h 32-bit signed value indicating Iq_ref for torque loop. Negative value is represented in two's complement iqRefClosedLoop = (IQ_REF_CLOSED_LOOP / 227) * Base_Current/8

7.8.5.29 ISD_STATE Register (Offset = 682h) [Reset = 0000h]

ISD_STATE is shown in Figure 7-117 and described in Table 7-93.

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ISD state Register

Figure 7-117 ISD_STATE Register
15141312111098
ISD_STATE
R-0h
76543210
ISD_STATE
R-0h
Table 7-93 ISD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ISD_STATER0h 16-bit value indicating current ISD state
0h = ISD_INIT
1h = ISD_MOTOR_STOP_CHECK
2h = ISD_ESTIM_INIT
3h = ISD_RUN_MOTOR_CHECK
4h = ISD_MOTOR_DIRECTION_CHECK
5h = ISD_COMPLETE
6h = ISD_FAULT

7.8.5.30 ISD_SPEED Register (Offset = 68Ch) [Reset = 00000000h]

ISD_SPEED is shown in Figure 7-118 and described in Table 7-94.

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ISD Speed Register

Figure 7-118 ISD_SPEED Register
313029282726252423222120191817161514131211109876543210
ISD_SPEED
R-0h
Table 7-94 ISD_SPEED Register Field Descriptions
BitFieldTypeResetDescription
31-0ISD_SPEEDR0h 32-bit value indicating calculated absolute speed during ISD state isdSpeed = (ISD_SPEED / 227) * max_Speed- In Hz

7.8.5.31 IPD_STATE Register (Offset = 6C0h) [Reset = 0000h]

IPD_STATE is shown in Figure 7-119 and described in Table 7-95.

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IPD state Register

Figure 7-119 IPD_STATE Register
15141312111098
IPD_STATE
R-0h
76543210
IPD_STATE
R-0h
Table 7-95 IPD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0IPD_STATER0h 16-bit value indicating current IPD state
0h = IPD_INIT
1h = IPD_VECTOR_CONFIG
2h = IPD_RUN
3h = IPD_SLOW_RISE_CLOCK
4h = IPD_SLOW_FALL_CLOCK
5h = IPD_WAIT_CURRENT_DECAY
6h = IPD_GET_TIMES
7h = IPD_SET_NEXT_VECTOR
8h = IPD_CALC_SECTOR_RISE
9h = IPD_CALC_ROTOR_POSITION
Ah = IPD_CALC_ANGLE
Bh = IPD_COMPLETE
Ch = IPD_FAULT

7.8.5.32 IPD_ANGLE Register (Offset = 704h) [Reset = 00000000h]

IPD_ANGLE is shown in Figure 7-120 and described in Table 7-96.

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Calculated IPD Angle Register

Figure 7-120 IPD_ANGLE Register
313029282726252423222120191817161514131211109876543210
IPD_ANGLE
R-0h
Table 7-96 IPD_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0IPD_ANGLER0h 32-bit signed value indicating measured IPD angle ipdAngle = (IPD_ANGLE / 227) * 360 (Degree)

7.8.5.33 ED Register (Offset = 74Ah) [Reset = 00000000h]

ED is shown in Figure 7-121 and described in Table 7-97.

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Estimated BEMF EQ Register

Figure 7-121 ED Register
313029282726252423222120191817161514131211109876543210
ED
R-0h
Table 7-97 ED Register Field Descriptions
BitFieldTypeResetDescription
31-0EDR0h 32-bit signed value indicating estimated ED. Negative value is represented in two's complement Ed = (ED / 227) * 60 / sqrt(3)

7.8.5.34 EQ Register (Offset = 74Ch) [Reset = 00000000h]

EQ is shown in Figure 7-122 and described in Table 7-98.

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Estimated BEMF ED Register

Figure 7-122 EQ Register
313029282726252423222120191817161514131211109876543210
EQ
R-0h
Table 7-98 EQ Register Field Descriptions
BitFieldTypeResetDescription
31-0EQR0h 32-bit signed value indicating estimated EQ. Negative value is represented in two's complement Eq = (EQ / 227) * 60 / sqrt(3)

7.8.5.35 SPEED_FDBK Register (Offset = 75Ah) [Reset = 00000000h]

SPEED_FDBK is shown in Figure 7-123 and described in Table 7-99.

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Speed Feedback Register

Figure 7-123 SPEED_FDBK Register
313029282726252423222120191817161514131211109876543210
SPEED_FDBK
R-0h
Table 7-99 SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_FDBKR0h 32-bit signed value indicating estimated rotor speed. The value is positive for OUTA-OUTB-OUTC and Negative and represented in two's complement for OUTA-OUTC-OUTB estimatedSpeed = (SPEED_FDBK / 227)*MAXIMUM_SPEED_HZ

7.8.5.36 THETA_EST Register (Offset = 75Eh) [Reset = 00000000h]

THETA_EST is shown in Figure 7-124 and described in Table 7-100.

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Estimated rotor Position Register

Figure 7-124 THETA_EST Register
313029282726252423222120191817161514131211109876543210
THETA_EST
R-0h
Table 7-100 THETA_EST Register Field Descriptions
BitFieldTypeResetDescription
31-0THETA_ESTR0h 32-bit signed value indicating estimated rotor angle. Negative value is represented in two's complement estimatedAngle = (THETA_EST / 227)*360 (Degree)