SLLSFQ7 November 2023 MCF8329A
PRODUCTION DATA
Table 7-42 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in Table 7-42 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 90h | FAULT_CONFIG1 | Fault Configuration1 | Section 7.7.4.1 |
| 92h | FAULT_CONFIG2 | Fault Configuration2 | Section 7.7.4.2 |
Complex bit access types are encoded to fit into small table cells. Table 7-43 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
FAULT_CONFIG1 is shown in Table 7-44.
Return to the Summary Table.
Register to configure fault settings1
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PARITY | R/W | 0h | Parity bit |
| 30-27 | ILIMIT | R/W | 0h | Phase Current Peak Limit (% of BASE_CURRENT)
0h = 5 % 1h = 10 % 2h = 15 % 3h = 20 % 4h = 25 % 5h = 30 % 6h = 40 % 7h = 50 % 8h = 60 % 9h = 65 % Ah = 70 % Bh = 75 % Ch = 80 % Dh = 85 % Eh = 90 % Fh = 95 % |
| 26-23 | HW_LOCK_ILIMIT | R/W | 0h | Comparator based lock detection current limit (% of BASE_CURRENT)
0h = 5 % 1h = 10 % 2h = 15 % 3h = 20 % 4h = 25 % 5h = 30 % 6h = 40 % 7h = 50 % 8h = 60 % 9h = 65 % Ah = 70 % Bh = 75 % Ch = 80 % Dh = 85 % Eh = 90 % Fh = 95 % |
| 22-19 | LOCK_ILIMIT | R/W | 0h | ADC based lock detection current threshold (% of BASE_CURRENT)
0h = 5 % 1h = 10 % 2h = 15 % 3h = 20 % 4h = 25 % 5h = 30 % 6h = 40 % 7h = 50 % 8h = 60 % 9h = 65 % Ah = 70 % Bh = 75 % Ch = 80 % Dh = 85 % Eh = 90 % Fh = 95 % |
| 18-15 | LOCK_ILIMIT_MODE | R/W | 0h | Lock current Limit Mode
0h = Ilimit lock detection causes latched fault; nfault active; Gate driver is tristated 1h = Ilimit lock detection causes latched fault; nfault active; Gate driver is tristated 2h = Ilimit lock detection causes latched fault; nfault active; Gate driver is in low side brake mode (All low side FETs are turned ON 3h = Ilimit lock detection causes latched fault; nfault active; Gate driver is in low side brake mode (All low side FETs are turned ON) 4h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFault active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFault active 6h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFault active 7h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFault active 8h = Ilimit lock detection current limit is in report only but no action is taken; nFault active 9h = ILIMIT LOCK is disabled Ah = ILIMIT LOCK is disabled Bh = ILIMIT LOCK is disabled Ch = ILIMIT LOCK is disabled Dh = ILIMIT LOCK is disabled Eh = ILIMIT LOCK is disabled Fh = ILIMIT LOCK is disabled |
| 14-11 | LOCK_ILIMIT_DEG | R/W | 0h | Lock detection current limit deglitch time
0h = No deglitch 1h = 0.1 ms 2h = 0.2 ms 3h = 0.5 ms 4h = 1 ms 5h = 2.5 ms 6h = 5 ms 7h = 7.5 ms 8h = 10 ms 9h = 25 ms Ah = 50 ms Bh = 75 ms Ch = 100 ms Dh = 200 ms Eh = 500 ms Fh = 1000 ms |
| 10-7 | LCK_RETRY | R/W | 0h | Lock detection retry time
0h = 300 ms 1h = 500 ms 2h = 1 s 3h = 2 s 4h = 3 s 5h = 4 s 6h = 5 s 7h = 6 s 8h = 7 s 9h = 8 s Ah = 9 s Bh = 10 s Ch = 11 s Dh = 12 s Eh = 13 s Fh = 14 s |
| 6-3 | MTR_LCK_MODE | R/W | 0h | Motor Lock Mode
0h = Motor lock detection causes latched fault; nfault active; Gate driver is tristated 1h = Motor lock detection causes latched fault; nfault active; Gate driver is tristated 2h = Motor lock detection causes latched fault; nfault active; Gate driver is in low side brake mode (All low side FETs are turned ON) 3h = Motor lock detection causes latched fault; nfault active; Gate driver is in low side brake mode (All low side FETs are turned ON) 4h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFault active 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated; nFault active 6h = Fault automatically cleared for AUTO_RETRY_TIMES after LCK_RETRY time; Gate driver is in low side brake mode (All low side FETs are turned ON); nFault active 7h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON); nFault active 8h = Motor lock detection current limit is in report only but no action is taken; nFault active 9h = Motor lock detection is disabled Ah = Motor lock detection is disabled Bh = Motor lock detection is disabled Ch = Motor lock detection is disabled Dh = Motor lock detection is disabled Eh = Motor lock detection is disabled Fh = Motor lock detection is disabled |
| 2 | IPD_TIMEOUT_FAULT_EN | R/W | 0h | IPD timeout fault Enable
0h = Disable 1h = Enable |
| 1 | IPD_FREQ_FAULT_EN | R/W | 0h | IPD frequency fault Enable
0h = Disable 1h = Enable |
| 0 | SATURATION_FLAGS_EN | R/W | 0h | Enable indication of current loop and speed loop saturation
0h = Disable 1h = Enable |
FAULT_CONFIG2 is shown in Table 7-45.
Return to the Summary Table.
Register to configure fault settings2
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PARITY | R/W | 0h | Parity bit |
| 30 | LOCK1_EN | R/W | 0h | Lock 1 (Abnormal Speed) Enable
0h = Disable 1h = Enable |
| 29 | LOCK2_EN | R/W | 0h | Lock 2 (Abnormal BEMF) Enable
0h = Disable 1h = Enable |
| 28 | LOCK3_EN | R/W | 0h | Lock 3 (No Motor) Enable
0h = Disable 1h = Enable |
| 27-25 | LOCK_ABN_SPEED | R/W | 0h | Abnormal speed lock threshold (% of MAX_SPEED)
0h = 130% 1h = 140% 2h = 150% 3h = 160% 4h = 170% 5h = 180% 6h = 190% 7h = 200% |
| 24-22 | ABNORMAL_BEMF_THR | R/W | 0h | Abnormal BEMF lock threshold (% of expected BEMF)
Expected BEMF = MOTOR_BEMF_CONST × Estimated Speed
0h = 40% 1h = 45% 2h = 50% 3h = 55% 4h = 60% 5h = 65% 6h = 67.5% 7h = 70% |
| 21-19 | NO_MTR_THR | R/W | 0h | No motor lock threshold (% of BASE_CURRENT)
0h = 1 % 1h = 2 % 2h = 3 % 3h = 4 % 4h = 5 % 5h = 7.5 % 6h = 10 % 7h = 20 % |
| 18-15 | HW_LOCK_ILIMIT_MODE | R/W | 0h | Hardware Lock Detection current mode
0h = Hardware Ilimit lock detection causes latched fault; nfault active; Gate driver is tristated 1h = Hardware Ilimit lock detection causes latched fault; nfault active; Gate driver is tristated 2h = Hardware Ilimit lock detection causes latched fault; nfault active; Gate driver is in low side brake mode (All low side FETs are turned ON) 3h = Hardware Ilimit lock detection causes latched fault; nfault active; Gate driver is in low side brake mode (All low side FETs are turned ON) 4h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated 5h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is tristated 6h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON) 7h = Fault automatically cleared after LCK_RETRY time. Number of retries limited to AUTO_RETRY_TIMES. If number of retries exceed AUTO_RETRY_TIMES, fault is latched; Gate driver is in low side brake mode (All low side FETs are turned ON) 8h = Hardware ILIMIT lock detection is in report only but no action is taken 9h = Hardware ILIMIT lock detection is disabled Ah = Hardware ILIMIT lock detection is disabled Bh = Hardware ILIMIT lock detection is disabled Ch = Hardware ILIMIT lock detection is disabled Dh = Hardware ILIMIT lock detection is disabled Eh = Hardware ILIMIT lock detection is disabled Fh = Hardware ILIMIT lock detection is disabled |
| 14-12 | HW_LOCK_ILIMIT_DEG | R/W | 0h | Hardware Lock Detection current limit deglitch time
0h = No Deglitch 1h = 1 us 2h = 2 us 3h = 3 us 4h = 4 us 5h = 5 us 6h = 6 us 7h = 7 us |
| 11 | VM_UV_OV_HYS | R/W | 0h | Hysteresis for DC bus under voltage and over voltage auto recovery
0h = 0.5V for UV and 1V for OV 1h = 1V for UV and 2V for OV |
| 10-8 | MIN_VM_MOTOR | R/W | 0h | DC Bus Undervoltage for running motor (V)
0h = No Limit 1h = 5.0 V 2h = 6.0 V 3h = 7.0 V 4h = 8.0 V 5h = 10.0 V 6h = 12.0 V 7h = 15.0 V |
| 7 | MIN_VM_MODE | R/W | 0h | DC Bus Undervoltage Fault Recovery Mode
0h = Latch on Undervoltage 1h = Automatic clear if voltage in bounds |
| 6-4 | MAX_VM_MOTOR | R/W | 0h | DC Bus Overvoltage for running motor
0h = No Limit 1h = 10.0 V 2h = 15.0 V 3h = 22.0 V 4h = 32.0 V 5h = 40.0 V 6h = 50.0 V 7h = 60.0 V |
| 3 | MAX_VM_MODE | R/W | 0h | DC Bus Overvoltage Fault Recovery Mode
0h = Latch on Overvoltage 1h = Automatic clear if voltage in bounds |
| 2-0 | AUTO_RETRY_TIMES | R/W | 0h | Automatic retry attempts. This is used only if any of the fault mode is configured as "retry"
0h = No Limit 1h = 2 2h = 3 3h = 5 4h = 7 5h = 10 6h = 15 7h = 20 |