SLLSFQ7 November 2023 MCF8329A
PRODUCTION DATA
Table 7-62 lists the memory-mapped registers for the Device_Control registers. All register offset addresses not listed in Table 7-62 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
EAh | ALGO_CTRL1 | Device Control Register | Section 7.8.4.1 |
Complex bit access types are encoded to fit into small table cells. Table 7-63 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
ALGO_CTRL1 is shown in Table 7-64.
Return to the Summary Table.
Control settings
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | EEPROM_WRT | R/W | 0h | Write the configuration to EEPROM |
30 | EEPROM_READ | R/W | 0h | Read the default configuration from EEPROM |
29 | CLR_FLT | W | 0h | Clears all faults |
28 | CLR_FLT_RETRY_COUNT | W | 0h | Clears fault retry count |
27-20 | EEPROM_WRITE_ACCESS_KEY | W | 0h | EEPROM write access key |
19-11 | FORCED_ALIGN_ANGLE | W | 0h | 9-bit value (in degrees) used during forced Align state ( FORCE_ALIGN_EN = 1) Angle applied = FORCED_ALIGN_ANGLE % 360deg |
10 | WATCHDOG_TICKLE | W | 0h | RAM bit to tickle watchdog in I2C mode. This bit should be written to 1b by external controller with in every EXT_WD_CONFIG. MCF8329 will reset this bit to 0b. |
9-0 | FLUX_MODE_REFERENCE | W | 0h | Sets ID Ref (% of BASE_CURRENT) when motor is in closed loop operation idRef = (FLUX_MODE_REFERENCE/500) * BASE_CURRENT if FLUX_MODE_REFERENCE < 500 idRef = (FLUX_MODE_REFERENCE - 1024)/500 * BASE_CURRENT if FLUX_MODE_REFERENCE > 524 Valid values are 0 to 500 and 524 to 1024 |