SLLSFQ7 November   2023 MCF8329A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Reference Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Bootstrap Capacitor Initial Charging
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Loop
        5. 7.3.11.5 Modulation Index Control
      12. 7.3.12 Maximum Torque Per Ampere (MTPA) Control
      13. 7.3.13 Flux Weakening Control
      14. 7.3.14 Motor Parameters
        1. 7.3.14.1 Motor Resistance
        2. 7.3.14.2 Motor Inductance
        3. 7.3.14.3 Motor Back-EMF constant
      15. 7.3.15 Motor Parameter Extraction Tool (MPET)
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 Active Braking
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behaviour During Fault
      23. 7.3.23 DC Bus Current Limit
      24. 7.3.24 Protections
        1. 7.3.24.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.24.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.24.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.24.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.24.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.24.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.24.7  Thermal Shutdown (OTSD)
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1001b to 1111b)
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.24.10 Motor Lock (MTR_LCK)
          1. 7.3.24.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.24.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.24.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.24.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.24.11 Motor Lock Detection
          1. 7.3.24.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.24.12 MPET Faults
        13. 7.3.24.13 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Internal_Algorithm_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Fault_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 Algorithm_Control Registers
      3. 7.8.3 System_Status Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2.       High speed (1.8 kHz) operation
        3.       Active Braking for faster deceleration
        4. 8.2.2.2 Dead Time compensation
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8.5 Algorithm_Variables Registers

Table 7-65 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not listed in Table 7-65 should be considered as reserved locations and the register contents should not be modified.

Table 7-65 ALGORITHM_VARIABLES Registers
OffsetAcronymRegister NameSection
196hALGORITHM_STATECurrent Algorithm State RegisterSection 7.8.5.1
19ChFG_SPEED_FDBKFG Speed Feedback RegisterSection 7.8.5.2
40EhBUS_CURRENTCalculated DC Bus Current RegisterSection 7.8.5.3
43ChPHASE_CURRENT_AMeasured Current on Phase A RegisterSection 7.8.5.4
43EhPHASE_CURRENT_BMeasured Current on Phase B RegisterSection 7.8.5.5
440hPHASE_CURRENT_CMeasured Current on Phase C RegisterSection 7.8.5.6
450hCSA_GAIN_FEEDBACKCSA Gain RegisterSection 7.8.5.7
458hVOLTAGE_GAIN_FEEDBACKVoltage Gain RegisterSection 7.8.5.8
45ChVM_VOLTAGEVM Voltage RegisterSection 7.8.5.9
460hPHASE_VOLTAGE_VAPhase A Voltage RegisterSection 7.8.5.10
462hPHASE_VOLTAGE_VBPhase B Voltage RegisterSection 7.8.5.11
464hPHASE_VOLTAGE_VCPhase C Voltage RegisterSection 7.8.5.12
4AAhSIN_COMMUTATION_ANGLESine of Commutation AngleSection 7.8.5.13
4AChCOS_COMMUTATION_ANGLECosine of Commutation AngleSection 7.8.5.14
4CChIALPHAIALPHA Current RegisterSection 7.8.5.15
4CEhIBETAIBETA Current RegisterSection 7.8.5.16
4D0hVALPHAVALPHA Voltage RegisterSection 7.8.5.17
4D2hVBETAVBETA Voltage RegisterSection 7.8.5.18
4DChIDMeasured d-axis Current RegisterSection 7.8.5.19
4DEhIQMeasured q-axis Current RegisterSection 7.8.5.20
4E0hVDVD Voltage RegisterSection 7.8.5.21
4E2hVQVQ Voltage RegisterSection 7.8.5.22
51AhIQ_REF_ROTOR_ALIGNAlign Current ReferenceSection 7.8.5.23
532hSPEED_REF_OPEN_LOOPOpen Loop Speed RegisterSection 7.8.5.24
542hIQ_REF_OPEN_LOOPOpen Loop Current ReferenceSection 7.8.5.25
5D0hSPEED_REF_CLOSED_LOOPSpeed Reference RegisterSection 7.8.5.26
60AhID_REF_CLOSED_LOOPReference for d-axis Current loop RegisterSection 7.8.5.27
60ChIQ_REF_CLOSED_LOOPReference q-axis for Current loop RegisterSection 7.8.5.28
6B0hISD_STATEISD State RegisterSection 7.8.5.29
6BAhISD_SPEEDISD Speed RegisterSection 7.8.5.30
6E4hIPD_STATEIPD State RegisterSection 7.8.5.31
71AhIPD_ANGLECalculated IPD Angle RegisterSection 7.8.5.32
75ChEDEstimated BEMF EQ RegisterSection 7.8.5.33
75EhEQEstimated BEMF ED RegisterSection 7.8.5.34
76EhSPEED_FDBKSpeed Feedback RegisterSection 7.8.5.35
774hTHETA_ESTEstimated rotor Position RegisterSection 7.8.5.36

Complex bit access types are encoded to fit into small table cells. Table 7-66 shows the codes that are used for access types in this section.

Table 7-66 Algorithm_Variables Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Reset or Default Value
-nValue after reset or the default value

7.8.5.1 ALGORITHM_STATE Register (Offset = 196h) [Reset = 0000h]

ALGORITHM_STATE is shown in Table 7-67.

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Current Algorithm State Register

Table 7-67 ALGORITHM_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ALGORITHM_STATER0h 16-bit value indicating current state of device
0h = MOTOR_IDLE
1h = MOTOR_ISD
2h = MOTOR_TRISTATE
3h = MOTOR_BRAKE_ON_START
4h = MOTOR_IPD
5h = MOTOR_SLOW_FIRST_CYCLE
6h = MOTOR_ALIGN
7h = MOTOR_OPEN_LOOP
8h = MOTOR_CLOSED_LOOP_UNALIGNED
9h = MOTOR_CLOSED_LOOP_ALIGNED
Ah = MOTOR_CLOSED_LOOP_ACTIVE_BRAKING
Bh = MOTOR_SOFT_STOP
Ch = MOTOR_RECIRCULATE_STOP
Dh = MOTOR_BRAKE_ON_STOP
Eh = MOTOR_FAULT
Fh = MOTOR_MPET_MOTOR_STOP_CHECK
10h = MOTOR_MPET_MOTOR_STOP_WAIT
11h = MOTOR_MPET_MOTOR_BRAKE
12h = MOTOR_MPET_ALGORITHM_PARAMETERS_INIT
13h = MOTOR_MPET_RL_MEASURE
14h = MOTOR_MPET_KE_MEASURE
15h = MOTOR_MPET_STALL_CURRENT_MEASURE
16h = MOTOR_MPET_TORQUE_MODE
17h = MOTOR_MPET_DONE
18h = MOTOR_MPET_FAULT

7.8.5.2 FG_SPEED_FDBK Register (Offset = 19Ch) [Reset = 00000000h]

FG_SPEED_FDBK is shown in Table 7-68.

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Speed Feedback from FG

Table 7-68 FG_SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0FG_SPEED_FDBKR0h 32-bit unsigned value indicating absolute value of estimated rotor speed
Estimated Speed = (FG_SPEED_FDBK / 227)*MAXIMUM_SPEED_HZ

7.8.5.3 BUS_CURRENT Register (Offset = 40Eh) [Reset = 00000000h]

BUS_CURRENT is shown in Table 7-69.

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Calculated Supply Current Register

Table 7-69 BUS_CURRENT Register Field Descriptions
BitFieldTypeResetDescription
31-0BUS_CURRENTR0h 32-bit signed value indicating bus current. Negative value is represented in two's complement
IBus = (BUS_CURRENT / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.4 PHASE_CURRENT_A Register (Offset = 43Ch) [Reset = 00000000h]

PHASE_CURRENT_A is shown in Table 7-70.

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Measured current on Phase A Register

Table 7-70 PHASE_CURRENT_A Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_AR0h 32-bit signed value indicating measured current on Phase A. Negative value is represented in two's complement
Ia = (PHASE_CURRENT_A / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.5 PHASE_CURRENT_B Register (Offset = 43Eh) [Reset = 00000000h]

PHASE_CURRENT_B is shown in Table 7-71.

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Measured current on Phase B Register

Table 7-71 PHASE_CURRENT_B Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_BR0h 32-bit signed value indicating measured current on Phase B. Negative value is represented in two's complement
IB = (PHASE_CURRENT_B / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.6 PHASE_CURRENT_C Register (Offset = 440h) [Reset = 00000000h]

PHASE_CURRENT_C is shown in Table 7-72.

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Measured current on Phase C Register

Table 7-72 PHASE_CURRENT_C Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_CURRENT_CR0h 32-bit signed value indicating measured current on Phase C. Negative value is represented in two's complement
IC = (PHASE_CURRENT_C / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.7 CSA_GAIN_FEEDBACK Register (Offset = 450h) [Reset = 0000h]

CSA_GAIN_FEEDBACK is shown in Table 7-73.

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CSA Gain Register

Table 7-73 CSA_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0CSA_GAIN_FEEDBACKR0h 16-bit value indicating current sense gain
0h = 40V/V
1h = 20V/V
2h = 10V/V
3h = 5V/V

7.8.5.8 VOLTAGE_GAIN_FEEDBACK Register (Offset = 458h) [Reset = 0000h]

VOLTAGE_GAIN_FEEDBACK is shown in Table 7-74.

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Voltage Gain Register

Table 7-74 VOLTAGE_GAIN_FEEDBACK Register Field Descriptions
BitFieldTypeResetDescription
15-0VOLTAGE_GAIN_FEEDBACKR0h 16-bit value indicating voltage gain
0h = 15V
1h = 30V
2h = 60V

7.8.5.9 VM_VOLTAGE Register (Offset = 45Ch) [Reset = 00000000h]

VM_VOLTAGE is shown in Table 7-75.

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Supply voltage register

Table 7-75 VM_VOLTAGE Register Field Descriptions
BitFieldTypeResetDescription
31-0VM_VOLTAGER0h 32-bit value indicating dc bus voltage
DC Bus Voltage = VM_VOLTAGE * 60 / 227

7.8.5.10 PHASE_VOLTAGE_VA Register (Offset = 460h) [Reset = 00000000h]

PHASE_VOLTAGE_VA is shown in Table 7-76.

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Phase A Voltage Register

Table 7-76 PHASE_VOLTAGE_VA Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VAR0h 32-bit value indicating Phase Voltage Va during ISD
Phase A voltage = PHASE_VOLTAGE_VA * 60 / (sqrt(3) * 227)

7.8.5.11 PHASE_VOLTAGE_VB Register (Offset = 462h) [Reset = 00000000h]

PHASE_VOLTAGE_VB is shown in Table 7-77.

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Phase B Voltage Register

Table 7-77 PHASE_VOLTAGE_VB Register Field Descriptions
BitFieldTypeResetDescription
31-0PHASE_VOLTAGE_VBR0h 32-bit value indicating Phase Voltage Vb during ISD
Phase B voltage = PHASE_VOLTAGE_VB * 60 / (sqrt(3) * 227)

7.8.5.12 PHASE_VOLTAGE_VC Register (Offset = 464h) [Reset = 0h]

PHASE_VOLTAGE_VC is shown in Table 7-78.

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Phase C Voltage Register

Table 7-78 PHASE_VOLTAGE_VC Register Field Descriptions
BitFieldTypeResetDescription
2PHASE_VOLTAGE_VCR0h 32-bit value indicating Phase Voltage Vc during ISD
Phase C voltage = PHASE_VOLTAGE_VC * 60 / (sqrt(3) * 227)
1-0RESERVEDR0h

7.8.5.13 SIN_COMMUTATION_ANGLE Register (Offset = 4AAh) [Reset = 00000000h]

SIN_COMMUTATION_ANGLE is shown in Table 7-79.

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Sine of Commutation Angle

Table 7-79 SIN_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0SIN_COMMUTATION_ANGLER0h 32-bit signed value indicating sine of commutation Angle. Negative value is represented in two's complement
SinCommutationAngle = (SIN_COMMUTATION_ANGLE / 227)

7.8.5.14 COS_COMMUTATION_ANGLE Register (Offset = 4ACh) [Reset = 00000000h]

COS_COMMUTATION_ANGLE is shown in Table 7-80.

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Cosine of Commutation Angle

Table 7-80 COS_COMMUTATION_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0COS_COMMUTATION_ANGLER0h 32-bit signed value indicating cosine of commutation Angle. Negative value is represented in two's complement
CosCommutationAngle = (COS_COMMUTATION_ANGLE / 227)

7.8.5.15 IALPHA Register (Offset = 4CCh) [Reset = 00000000h]

IALPHA is shown in Table 7-81.

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IALPHA Current Register

Table 7-81 IALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0IALPHAR0h 32-bit signed value indicating calculated IALPHA. Negative value is represented in two's complement
IAlpha = (IALPHA / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.16 IBETA Register (Offset = 4CEh) [Reset = 00000000h]

IBETA is shown in Table 7-82.

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IBETA Current Register

Table 7-82 IBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0IBETAR0h 32-bit signed value indicating calculated IBETA. Negative value is represented in two's complement
IBeta = (IBETA / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.17 VALPHA Register (Offset = 4D0h) [Reset = 00000000h]

VALPHA is shown in Table 7-83.

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VALPHA Voltage Register

Table 7-83 VALPHA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALPHAR0h 32-bit signed value indicating calculated VALPHA. Negative value is represented in two's complement
VAlpha = (VALPHA / 227) * 60 / sqrt(3)

7.8.5.18 VBETA Register (Offset = 4D2h) [Reset = 00000000h]

VBETA is shown in Table 7-84.

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VBETA Voltage Register

Table 7-84 VBETA Register Field Descriptions
BitFieldTypeResetDescription
31-0VBETAR0h 32-bit signed value indicating calculated VBETA. Negative value is represented in two's complement
VBeta = (VBETA / 227) * 60 / sqrt(3)

7.8.5.19 ID Register (Offset = 4DCh) [Reset = 00000000h]

ID is shown in Table 7-85.

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Measured d-axis Current Register

Table 7-85 ID Register Field Descriptions
BitFieldTypeResetDescription
31-0IDR0h 32-bit signed value indicating estimated Id. Negative value is represented in two's complement
Id = (ID / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.20 IQ Register (Offset = 4DEh) [Reset = 00000000h]

IQ is shown in Table 7-86.

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Measured q-axis Current Register

Table 7-86 IQ Register Field Descriptions
BitFieldTypeResetDescription
31-0IQR0h 32-bit signed value indicating estimated Iq. Negative value is represented in two's complement
Iq = (IQ / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.21 VD Register (Offset = 4E0h) [Reset = 00000000h]

VD is shown in Table 7-87.

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VD Voltage Register

Table 7-87 VD Register Field Descriptions
BitFieldTypeResetDescription
31-0VDR0h 32-bit signed value indicating applied Vd. Negative value is represented in two's complement
Vd = (VD / 227) * 60 / sqrt(3)

7.8.5.22 VQ Register (Offset = 4E2h) [Reset = 00000000h]

VQ is shown in Table 7-88.

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VQ Voltage Register

Table 7-88 VQ Register Field Descriptions
BitFieldTypeResetDescription
31-0VQR0h 32-bit signed value indicating applied Vq. Negative value is represented in two's complement
Vq = (VQ / 227) * 60 / sqrt(3)

7.8.5.23 IQ_REF_ROTOR_ALIGN Register (Offset = 51Ah) [Reset = 00000000h]

IQ_REF_ROTOR_ALIGN is shown in Table 7-89.

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Align Current Reference

Table 7-89 IQ_REF_ROTOR_ALIGN Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_ROTOR_ALIGNR0h 32-bit signed value indicating Align Current Reference. Negative value is represented in two's complement
IqRefRotorAlign = (IQ_REF_ROTOR_ALIGN / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.24 SPEED_REF_OPEN_LOOP Register (Offset = 532h) [Reset = 00000000h]

SPEED_REF_OPEN_LOOP is shown in Table 7-90.

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Speed at which motor transitions to close loop

Table 7-90 SPEED_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_OPEN_LOOPR0h 32-bit signed value indicating Open Loop Speed. The value is positive for OUTA-OUTB-OUTC and Negative and represented in two's complement for OUTA-OUTC-OUTB
OpenLoopSpeedRef = (SPEED_REF_OPEN_LOOP / 227) * max_Speed- In Hz

7.8.5.25 IQ_REF_OPEN_LOOP Register (Offset = 542h) [Reset = 00000000h]

IQ_REF_OPEN_LOOP is shown in Table 7-91.

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Open Loop Current Reference

Table 7-91 IQ_REF_OPEN_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_OPEN_LOOPR0h 32-bit signed value indicating Open Loop Current Reference. Negative value is represented in two's complement
IqRefOpenLoop = (IQ_REF_OPEN_LOOP / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.26 SPEED_REF_CLOSED_LOOP Register (Offset = 5D0h) [Reset = 00000000h]

SPEED_REF_CLOSED_LOOP is shown in Table 7-92.

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Speed Reference Register

Table 7-92 SPEED_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_REF_CLOSED_LOOPR0h 32-bit signed value indicating reference for closed loop. Negative and represented in two's complement
In Speed Control mode, Speed Reference in closed loop (Hz) = (SPEED_REF_CLOSED_LOOP/ 227) * MAX_SPEED (Hz)
In Power Control mode, Power Reference in closed loop (watts ) = (SPEED_REF_CLOSED_LOOP/ 227) * MAX_POWER (Watts)
In Current Control mode, IQ current reference in closed loop (A) = (SPEED_REF_CLOSED_LOOP / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.27 ID_REF_CLOSED_LOOP Register (Offset = 60Ah) [Reset = 00000000h]

ID_REF_CLOSED_LOOP is shown in Table 7-93.

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Reference for Current Loop Register

Table 7-93 ID_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0ID_REF_CLOSED_LOOPR0h 32-bit signed value indicating Id_ref for flux loop. Negative value is represented in two's complement
IdRefClosedLoop = (ID_REF_CLOSED_LOOP / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.28 IQ_REF_CLOSED_LOOP Register (Offset = 60Ch) [Reset = 00000000h]

IQ_REF_CLOSED_LOOP is shown in Table 7-94.

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Reference for Current Loop Register

Table 7-94 IQ_REF_CLOSED_LOOP Register Field Descriptions
BitFieldTypeResetDescription
31-0IQ_REF_CLOSED_LOOPR0h 32-bit signed value indicating Iq_ref for torque loop. Negative value is represented in two's complement
IqRefClosedLoop = (IQ_REF_CLOSED_LOOP / 227) * Base_Current/(2CSA_GAIN_FEEDBACK)

7.8.5.29 ISD_STATE Register (Offset = 6B0h) [Reset = 0000h]

ISD_STATE is shown in Table 7-95.

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ISD state Register

Table 7-95 ISD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0ISD_STATER0h 16-bit value indicating current ISD state
0h = ISD_INIT
1h = ISD_MOTOR_STOP_CHECK
2h = ISD_ESTIM_INIT
3h = ISD_RUN_MOTOR_CHECK
4h = ISD_MOTOR_DIRECTION_CHECK
5h = ISD_COMPLETE
6h = ISD_FAULT

7.8.5.30 ISD_SPEED Register (Offset = 6BAh) [Reset = 00000000h]

ISD_SPEED is shown in Table 7-96.

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ISD Speed Register

Table 7-96 ISD_SPEED Register Field Descriptions
BitFieldTypeResetDescription
31-0ISD_SPEEDR0h 32-bit value indicating calculated absolute speed during ISD state
Isd speed = (ISD_SPEED / 227) * max_Speed- In Hz

7.8.5.31 IPD_STATE Register (Offset = 6E4h) [Reset = 0000h]

IPD_STATE is shown in Table 7-97.

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IPD state Register

Table 7-97 IPD_STATE Register Field Descriptions
BitFieldTypeResetDescription
15-0IPD_STATER0h 16-bit value indicating current IPD state
0h = IPD_INIT
1h = IPD_VECTOR_CONFIG
2h = IPD_RUN
3h = IPD_SLOW_RISE_CLOCK
4h = IPD_SLOW_FALL_CLOCK
5h = IPD_WAIT_CURRENT_DECAY
6h = IPD_GET_TIMES
7h = IPD_SET_NEXT_VECTOR
8h = IPD_CALC_SECTOR_RISE
9h = IPD_CALC_ROTOR_POSITION
Ah = IPD_CALC_ANGLE
Bh = IPD_COMPLETE
Ch = IPD_FAULT

7.8.5.32 IPD_ANGLE Register (Offset = 71Ah) [Reset = 00000000h]

IPD_ANGLE is shown in Table 7-98.

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Calculated IPD Angle Register

Table 7-98 IPD_ANGLE Register Field Descriptions
BitFieldTypeResetDescription
31-0IPD_ANGLER0h 32-bit value indicating measured IPD angle
IpdAngle = (IPD_ANGLE / 227) * 360 (Degree)

7.8.5.33 ED Register (Offset = 75Ch) [Reset = 00000000h]

ED is shown in Table 7-99.

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Estimated BEMF EQ Register

Table 7-99 ED Register Field Descriptions
BitFieldTypeResetDescription
31-0EDR0h 32-bit signed value indicating estimated ED. Negative value is represented in two's complement
Ed = (ED / 227) * 60 / sqrt(3)

7.8.5.34 EQ Register (Offset = 75Eh) [Reset = 00000000h]

EQ is shown in Table 7-100.

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Estimated BEMF ED Register

Table 7-100 EQ Register Field Descriptions
BitFieldTypeResetDescription
31-0EQR0h 32-bit signed value indicating estimated EQ. Negative value is represented in two's complement
Eq = (EQ / 227) * 60 / sqrt(3)

7.8.5.35 SPEED_FDBK Register (Offset = 76Eh) [Reset = 00000000h]

SPEED_FDBK is shown in Table 7-101.

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Speed Feedback Register

Table 7-101 SPEED_FDBK Register Field Descriptions
BitFieldTypeResetDescription
31-0SPEED_FDBKR0h 32-bit signed value indicating estimated rotor speed. The value is positive for OUTA-OUTB-OUTC and Negative and represented in two's complement for OUTA-OUTC-OUTB
Estimated speed = (SPEED_FDBK / 227)*MAXIMUM_SPEED_HZ

7.8.5.36 THETA_EST Register (Offset = 774h) [Reset = 00000000h]

THETA_EST is shown in Table 7-102.

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Estimated rotor Position Register

Table 7-102 THETA_EST Register Field Descriptions
BitFieldTypeResetDescription
31-0THETA_ESTR0h 32-bit signed value indicating estimated rotor angle. Negative value is represented in two's complement
Estimated angle = (THETA_EST / 227)*360 (Degree)