SLLSFQ7 November   2023 MCF8329A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Reference Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Bootstrap Capacitor Initial Charging
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Loop
        5. 7.3.11.5 Modulation Index Control
      12. 7.3.12 Maximum Torque Per Ampere (MTPA) Control
      13. 7.3.13 Flux Weakening Control
      14. 7.3.14 Motor Parameters
        1. 7.3.14.1 Motor Resistance
        2. 7.3.14.2 Motor Inductance
        3. 7.3.14.3 Motor Back-EMF constant
      15. 7.3.15 Motor Parameter Extraction Tool (MPET)
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 Active Braking
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behaviour During Fault
      23. 7.3.23 DC Bus Current Limit
      24. 7.3.24 Protections
        1. 7.3.24.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.24.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.24.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.24.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.24.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.24.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.24.7  Thermal Shutdown (OTSD)
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1001b to 1111b)
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.24.10 Motor Lock (MTR_LCK)
          1. 7.3.24.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.24.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.24.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.24.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.24.11 Motor Lock Detection
          1. 7.3.24.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.24.12 MPET Faults
        13. 7.3.24.13 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Internal_Algorithm_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Fault_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 Algorithm_Control Registers
      3. 7.8.3 System_Status Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2.       High speed (1.8 kHz) operation
        3.       Active Braking for faster deceleration
        4. 8.2.2.2 Dead Time compensation
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8.2 Algorithm_Control Registers

Table 7-50 lists the memory-mapped registers for the Algorithm_Control registers. All register offset addresses not listed in Table 7-50 should be considered as reserved locations and the register contents should not be modified.

Table 7-50 ALGORITHM_CONTROL Registers
OffsetAcronymRegister NameSection
EChALGO_DEBUG1Algorithm Control RegisterSection 7.8.2.1
EEhALGO_DEBUG2Algorithm Control RegisterSection 7.8.2.2
F0hCURRENT_PICurrent PI Controller usedSection 7.8.2.3
F2hSPEED_PISpeed PI controller usedSection 7.8.2.4
F4hDAC_1DAC1 Control RegisterSection 7.8.2.5

Complex bit access types are encoded to fit into small table cells. Table 7-51 shows the codes that are used for access types in this section.

Table 7-51 Algorithm_Control Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.8.2.1 ALGO_DEBUG1 Register (Offset = ECh) [Reset = 00000000h]

ALGO_DEBUG1 is shown in Table 7-52.

Return to the Summary Table.

Algorithm control register for debug

Table 7-52 ALGO_DEBUG1 Register Field Descriptions
BitFieldTypeResetDescription
31SPEED_OVER_RIDEW0h Use to control the SPEED_MODE bits.
If SPEED_OVER_RIDE = '1', Duty command can be written by the user through I2C serial interface.
0h = SPEED_MODE using Analog/PWM mode
1h = SPEED_MODE using DIGITAL_SPEED_CTRL
30-16DIGITAL_SPEED_CTRLW0h Digital Duty Command through I2C
If OVERRIDE = 1, then SPEED_MODE is using DIGITAL_SPEED_CTRL
15CLOSED_LOOP_DISW0h Use to disable Closed loop
0h = Enable Closed Loop
1h = Disable Closed loop, motor commutation in open loop
14FORCE_ALIGN_ENW0h Force Align State Enable
0h = Disable Force Align state, device comes out of align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN
1h = Enable Force Align state, device stays in align state if MTR_STARTUP is selected as ALIGN or DOUBLE ALIGN
13FORCE_SLOW_FIRST_CYCLE_ENW0h Force Slow First Cycle Enable
0h = Disable Force Slow First Cycle state, device comes out of slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE
1h = Enable Force Slow First Cycle state, device stays in slow first cycle state if MTR_STARTUP is selected as SLOW FIRST CYCLE
12FORCE_IPD_ENW0h Force IPD Enable
0h = Disable Force IPD state, device comes out of IPD state if MTR_STARTUP is selected as IPD
1h = Enable Force IPD state, device stays in IPD state if MTR_STARTUP is selected as IPD
11FORCE_ISD_ENW0h Force ISD enable
0h = Disable Force ISD state, device comes out of ISD state if ISD_EN is set
1h = Enable Force ISD state, device stays in ISD state if ISD_EN is set
10FORCE_ALIGN_ANGLE_SRC_SELW0h Force Align Angle State Source Select
0h = Force Align Angle defined by ALIGN_ANGLE
1h = Force Align Angle defined by FORCED_ALIGN_ANGLE
9-0RESERVEDW0h Reserved

7.8.2.2 ALGO_DEBUG2 Register (Offset = EEh) [Reset = 00000000h]

ALGO_DEBUG2 is shown in Table 7-53.

Return to the Summary Table.

Algorithm control register for debug

Table 7-53 ALGO_DEBUG2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDW0h Reserved
30-28FORCE_RECIRCULATE_STOP_SECTORW0h use to do the recirculation at specific sector during force motor stop condition
0h = The last sector before stop condition
1h = Sector1
2h = Sector2
3h = Sector3
4h = Sector4
5h = Sector5
6h = Sector6
7h = The last sector before stop condition
27FORCE_RECIRCULATE_STOP_ENW0h Force recirculate stop Enable
0h = Enable Force recirculate stop
1h = Disable Force recirculate stop
26CURRENT_LOOP_DISW0h Use to control the FORCE_VD_CURRENT_LOOP_DIS and FORCE_VQ_CURRENT_LOOP_DIS. If CURRENT_LOOP_DIS = '1', Current loop and speed loop are disabled
0h = Enable Current Loop
1h = Disable Current Loop
25-16FORCE_VD_CURRENT_LOOP_DISW0h Sets Vd when current loop and speed loop are disabled
If CURRENT_LOOP_DIS = 0b1, then Vd is control using FORCE_VD_CURRENT_LOOP_DIS
mdRef = (FORCE_VD_CURRENT_LOOP_DIS /500) if FORCE_VD_CURRENT_LOOP_DIS < 500
(FORCE_VD_CURRENT_LOOP_DIS - 1024)/500 if FORCE_VD_CURRENT_LOOP_DIS > 524
Valid values: 0 to 500 and 524 to 1024
15-6FORCE_VQ_CURRENT_LOOP_DISW0h Sets Vq when current loop and speed loop are disabled
If CURRENT_LOOP_DIS = 0b1, then Vq is control using FORCE_VQ_CURRENT_LOOP_DIS
mqRef = (FORCE_VQ_CURRENT_LOOP_DIS /500) if FORCE_VQ_CURRENT_LOOP_DIS < 500
(FORCE_VQ_CURRENT_LOOP_DIS - 1024)/500 if FORCE_VQ_CURRENT_LOOP_DIS > 524
Valid values: 0 to 500 and 524 to 1024
5MPET_CMDW0h Initiates motor parameter measurement routine when set to 1
4RESERVEDW0h Reserved
3RESERVEDW0h Reserved
2MPET_KEW0h Enables motor BEMF constant measurement during motor parameter measurement routine
0h = Disables Motor BEMF constant measurement during motor parameter measurement routine
1h = Enable Motor BEMF constant measurement during motor parameter measurement routine
1MPET_MECHW0h Enables motor mechanical parameter measurement during motor parameter measurement routine
0h = Disables Motor mechanical parameter measurement during motor parameter measurement routine
1h = Enable Motor mechanical parameter measurement during motor parameter measurement routine
0MPET_WRITE_SHADOWW0h Write measured parameters to shadow register when set to 1

7.8.2.3 CURRENT_PI Register (Offset = F0h) [Reset = 00000000h]

CURRENT_PI is shown in Table 7-54.

Return to the Summary Table.

Current PI controller used

Table 7-54 CURRENT_PI Register Field Descriptions
BitFieldTypeResetDescription
31-16CURRENT_LOOP_KIR0h 10 bit for current loop ki
Same Scaling as CURR_LOOP_KI
15-0CURRENT_LOOP_KPR0h 10 bit for current loop kp
Same Scaling as CURR_LOOP_KP

7.8.2.4 SPEED_PI Register (Offset = F2h) [Reset = 00000000h]

SPEED_PI is shown in Table 7-55.

Return to the Summary Table.

Speed PI controller used

Table 7-55 SPEED_PI Register Field Descriptions
BitFieldTypeResetDescription
31-16SPEED_LOOP_KIR0h 10 bit for speed loop ki
Same Scaling as SPD_LOOP_KI
15-0SPEED_LOOP_KPR0h 10 bit for speed loop kp
Same Scaling as SPD_LOOP_KP

7.8.2.5 DAC_1 Register (Offset = F4h) [Reset = 00000000h]

DAC_1 is shown in Table 7-56.

Return to the Summary Table.

DAC1 Control Register

Table 7-56 DAC_1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h Reserved
20-17DACOUT1_ENUM_SCALINGW0h Multiplication Factor for DACOUT1
Algorithm Variable extracted from the address contained in DACOUT1_VAR_ADDR multiplied with 2DACOUT1_ENUM_SCALING
DACOUT1_ENUM_SCALING comes into effect only if DACOUT1_SCALING is zero
16-13DACOUT1_SCALINGW0h Scaling factor for DACOUT1
Algorithm Variable extracted from the address contained in DACOUT1_VAR_ADDR scaled with DACOUT1_SCALING / 8. Actual voltage depends on DACOUT1_UNIPOLAR
If DACOUT1_UNIPOLAR = 1, 0V == 0pu of algorithm Variable * DACOUT1_SCALING / 8, 3V == 1pu of algorithm Variable * DACOUT1_SCALING / 8
If DACOUT1_UNIPOLAR = 0, 0V == -1pu of algorithm Variable * DACOUT1_SCALING / 8, 3V == 1pu of algorithm Variable * DACOUT1_SCALING / 8
0h = Treated s Enum with max value being 31
1h = 1 / 8
2h = 2 / 8
3h = 3 / 8
4h = 4 / 8
5h = 5 / 8
6h = 6 / 8
7h = 7 / 8
8h = 8 / 8
9h = 9 / 8
Ah = 10 / 8
Bh = 11 / 8
Ch = 12 / 8
Dh = 13 / 8
Eh = 14 / 8
Fh = 15 / 8
12DACOUT1_UNIPOLARW0h Configures output of DACOUT1
If DACOUT1_UNIPOLAR = 1, 0V == 0pu of algorithm Variable * DACOUT1_SCALING / 16, 3V == 1pu of algorithm Variable * DACOUT1_SCALING / 16
If DACOUT1_UNIPOLAR = 0, 0V == -1pu of algorithm Variable * DACOUT1_SCALING / 16, 3V == 1pu of algorithm Variable * DACOUT1_SCALING / 16
0h = Bipolar (Offset of 1.5 V)
1h = Unipolar (No Offset)
11-0DACOUT1_VAR_ADDRR/W0h 12-bit address of variable to be monitored