SLLSFQ7 November   2023 MCF8329A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Reference Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Bootstrap Capacitor Initial Charging
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Loop
        5. 7.3.11.5 Modulation Index Control
      12. 7.3.12 Maximum Torque Per Ampere (MTPA) Control
      13. 7.3.13 Flux Weakening Control
      14. 7.3.14 Motor Parameters
        1. 7.3.14.1 Motor Resistance
        2. 7.3.14.2 Motor Inductance
        3. 7.3.14.3 Motor Back-EMF constant
      15. 7.3.15 Motor Parameter Extraction Tool (MPET)
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 Active Braking
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behaviour During Fault
      23. 7.3.23 DC Bus Current Limit
      24. 7.3.24 Protections
        1. 7.3.24.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.24.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.24.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.24.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.24.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.24.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.24.7  Thermal Shutdown (OTSD)
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1001b to 1111b)
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.24.10 Motor Lock (MTR_LCK)
          1. 7.3.24.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.24.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.24.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.24.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.24.11 Motor Lock Detection
          1. 7.3.24.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.24.12 MPET Faults
        13. 7.3.24.13 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Internal_Algorithm_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Fault_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 Algorithm_Control Registers
      3. 7.8.3 System_Status Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2.       High speed (1.8 kHz) operation
        3.       Active Braking for faster deceleration
        4. 8.2.2.2 Dead Time compensation
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.2 Internal_Algorithm_Configuration Registers

Table 7-30 lists the memory-mapped registers for the Internal_Algorithm_Configuration registers. All register offset addresses not listed in Table 7-30 should be considered as reserved locations and the register contents should not be modified.

Table 7-30 INTERNAL_ALGORITHM_CONFIGURATION Registers
OffsetAcronymRegister NameSection
A0hINT_ALGO_1Internal Algorithm Configuration1Section 7.7.2.1
A2hINT_ALGO_2Internal Algorithm Configuration2Section 7.7.2.2

Complex bit access types are encoded to fit into small table cells. Table 7-31 shows the codes that are used for access types in this section.

Table 7-31 Internal_Algorithm_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.2.1 INT_ALGO_1 Register (Offset = A0h) [Reset = 00000000h]

INT_ALGO_1 is shown in Table 7-32.

Return to the Summary Table.

Register to configure internal algorithm parameters1

Table 7-32 INT_ALGO_1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-29ACTIVE_BRAKE_SPEED_DELTA_LIMIT_EXITR/W0h Speed Reference difference (% of MAX_SPEED) to come out of Active Brake state
0h = 2.5%
1h = 5%
2h = 7.5%
3h = 10%
28-27SPEED_PIN_GLITCH_FILTERR/W0h Glitch filter applied on SPEED/WAKE pin in PWM and Frequency input mode
0h = No Glitch Filter
1h = 0.2 µs
2h = 0.5 µs
3h = 1.0 µs
26FAST_ISD_ENR/W0h Enable fast speed detection during ISD
0h = Disable Fast ISD
1h = Enable Fast ISD
25-24ISD_STOP_TIMER/W0h Persistence time for declaring motor has stopped
0h = 1 ms
1h = 5 ms
2h = 50 ms
3h = 100 ms
23-22ISD_RUN_TIMER/W0h Persistence time for declaring motor is running
0h = 1 ms
1h = 5 ms
2h = 50 ms
3h = 100 ms
21-20ISD_TIMEOUTR/W0h Timeout in case ISD is unable to reliably detect speed or direction
0h = 500ms
1h = 750 ms
2h = 1000 ms
3h = 2000 ms
19-17AUTO_HANDOFF_MIN_BEMFR/W0h Minimum BEMF for auto handoff
0h = 0 mV
1h = 100 mV
2h = 200 mV
3h = 500 mV
4h = 1000 mV
5h = 2000 mV
6h = 2500 mV
7h = 3000 mV
16-15RESERVEDR/W0h Reserved
14-13RESERVEDR/W0h Reserved
12-11RESERVEDR/W0h Reserved
10-8MPET_OPEN_LOOP_CURR_REFR/W0h Open Loop Current Reference for MPET (% of BASE_CURRENT)
0h = 10%
1h = 20%
2h = 30%
3h = 40%
4h = 50%
5h = 60%
6h = 70%
7h = 80%
7-6MPET_OPEN_LOOP_SPEED_REFR/W0h Open Loop Speed Reference for MPET (% of MAXIMUM_SPEED)
0h = 15%
1h = 25%
2h = 35%
3h = 50%
5-3MPET_OPEN_LOOP_SLEW_RATER/W0h Open loop acceleration for MPET
0h = 0.1 Hz/s
1h = 0.5 Hz/s
2h = 1 Hz/s
3h = 2 Hz/s
4h = 3 Hz/s
5h = 5 Hz/s
6h = 10 Hz/s
7h = 20 Hz/s
2-0REV_DRV_OPEN_LOOP_DECR/W0h % of open loop acceleration to be applied during open loop deceleration in reverse drive
0h = 50%
1h = 60%
2h = 70%
3h = 80%
4h = 90%
5h = 100%
6h = 125%
7h = 150%

7.7.2.2 INT_ALGO_2 Register (Offset = A2h) [Reset = 00000000h]

INT_ALGO_2 is shown in Table 7-33.

Return to the Summary Table.

Register to configure internal algorithm parameters2

Table 7-33 INT_ALGO_2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-21FLUX_WEAKENING_KPR/W0h 10-bit value for flux weakening Kp
FLUX_WEAKENING_KP is divided in 2 sections
SCALE(9:8) and VALUE(7:0)
Kp = 0.1 × VALUE / 10^SCALE.
20-11FLUX_WEAKENING_KIR/W0h 10-bit value for flux weakening Ki
FLUX_WEAKENING_KI is divided in 2 sections
SCALE(9:8) and VALUE(7:0)
Ki = 10.0 × VALUE / 10^SCALE).
10FLUX_WEAKENING_ENR/W0h Flux Weakening Enable
0h = Flux Weakening Disabled
1h = Flux Weakening Enabled
9-6CL_SLOW_ACCR/W0h Close loop acceleration when estimator is not yet fully aligned just after transition to closed loop
Speed Mode ( Hz/s)
Power Mode (W/s)
Current Mode (A/s)
Voltage Mode(0.1% modulation index per second)
0h = 0.1
1h = 1
2h = 2
3h = 3
4h = 5
5h = 10
6h = 20
7h = 30
8h = 40
9h = 50
Ah = 100
Bh = 200
Ch = 500
Dh = 750
Eh = 1000
Fh = 2000
5-3ACTIVE_BRAKE_BUS_CURRENT_SLEW_RATER/W0h Bus Current slew rate during active braking (A/s)
0h = 10 A/s
1h = 50 A/s
2h = 100 A/s
3h = 250 A/s
4h = 500 A/s
5h = 1000 A/s
6h = 5000 A/s
7h = No Limit
2RESERVEDR/W0h Reserved
1MPET_KE_MEAS_PARAMETER_SELECTR/W0h MPET parameters selection
0h = Configured parameters for normal motor operation (OL_ACC_A1, OL_ACC_A2 for slew rate, OL_ILIMIT for current reference and OPN_CL_HANDOFF_THR for speed reference).
1h = MPET specific parameters (MPET_OPEN_LOOP_SLEW_RATE for slew rate, MPET_OPEN_LOOP_CURR_REF for current reference, MPET_OPEN_LOOP_SPEED_REF for speed reference).
0IPD_HIGH_RESOLUTION_ENR/W0h IPD high resolution enable
0h = Disable
1h = Enable