SLLSFQ7 November   2023 MCF8329A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Reference Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Bootstrap Capacitor Initial Charging
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed loop accelerate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Power Loop
        5. 7.3.11.5 Modulation Index Control
      12. 7.3.12 Maximum Torque Per Ampere (MTPA) Control
      13. 7.3.13 Flux Weakening Control
      14. 7.3.14 Motor Parameters
        1. 7.3.14.1 Motor Resistance
        2. 7.3.14.2 Motor Inductance
        3. 7.3.14.3 Motor Back-EMF constant
      15. 7.3.15 Motor Parameter Extraction Tool (MPET)
      16. 7.3.16 Anti-Voltage Surge (AVS)
      17. 7.3.17 Output PWM Switching Frequency
      18. 7.3.18 Active Braking
      19. 7.3.19 Dead Time Compensation
      20. 7.3.20 Voltage Sense Scaling
      21. 7.3.21 Motor Stop Options
        1. 7.3.21.1 Coast (Hi-Z) Mode
        2. 7.3.21.2 Recirculation Mode
        3. 7.3.21.3 Low-Side Braking
        4. 7.3.21.4 Active Spin-Down
      22. 7.3.22 FG Configuration
        1. 7.3.22.1 FG Output Frequency
        2. 7.3.22.2 FG in Open-Loop
        3. 7.3.22.3 FG During Motor Stop
        4. 7.3.22.4 FG Behaviour During Fault
      23. 7.3.23 DC Bus Current Limit
      24. 7.3.24 Protections
        1. 7.3.24.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.24.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.24.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.24.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.24.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.24.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.24.7  Thermal Shutdown (OTSD)
        8. 7.3.24.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.24.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1001b to 1111b)
        9. 7.3.24.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.24.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.24.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.24.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.24.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.24.10 Motor Lock (MTR_LCK)
          1. 7.3.24.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.24.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.24.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.24.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.24.11 Motor Lock Detection
          1. 7.3.24.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.24.11.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.24.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.24.12 MPET Faults
        13. 7.3.24.13 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Internal_Algorithm_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Fault_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 Algorithm_Control Registers
      3. 7.8.3 System_Status Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2.       High speed (1.8 kHz) operation
        3.       Active Braking for faster deceleration
        4. 8.2.2.2 Dead Time compensation
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.24 Protections

The MCF8329A is protected from a host of fault events including motor lock, PVDD under-voltage, AVDD under-voltage, GVDD under-voltage, bootstrap under-voltage, over temperature and overcurrent events. Table 7-5 summarizes the response, recovery modes, gate driver status, reporting mechanism for different faults.

Note:
  1. Actionable and report only faults (latched or retry) are always reported on nFAULT pin (as logic low).
  2. Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT or through a power recycle. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses.
  3. Recovery refers only to state of gate driver after the fault condition is removed. Automatic indicates that the device automatically recovers (and gate driver outputs and hence external FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) or through a power recycle.
  4. The GVDD under-voltage, BST under voltage, VDS OCP, SENSE OCP faults can take up to 200-ms after fault response (gate driver outputs pulled low to put the external FETs in Hi-Z) to be reported on nFAULT pin (as logic low).
  5. Latched faults can take up to 200-ms after CLR_FLT command is issued (over I2C) to be cleared.
  6. CLR_FLT command (over I2C) can clean all the faults including latched, retry and auto recovery faults.
Table 7-5 Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT GATE DRIVER LOGIC RECOVERY
PVDD under-voltage
(PVDD_UV) 		VPVDD < VPVDD_UV — nFAULT Disabled Disabled Automatic:
VPVDD > VPVDD_UV
AVDD POR
(AVDD_POR)		 VAVDD < VAVDD_POR — nFAULT Disabled Disabled Automatic:
VAVDD > VAVDD_POR
GVDD under-voltage
(GVDD_UV)		 VGVDD < VGVDD_UV GVDD_UV_MODE = 0b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Latched:
CLR_FLT
GVDD_UV_MODE = 1b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Retry:
tLCK_RETRY
BSTx under-voltage
(BST_UV) 		VBSTx - VSHx < VBST_UV

DIS_BST_FLT = 0b

BST_UV_MODE = 0b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Latched:
CLR_FLT

DIS_BST_FLT = 0b

BST_UV_MODE = 1b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Retry:
tLCK_RETRY
VDS overcurrent
(VDS_OCP) 		VDS > VSEL_VDS_LVL

DIS_VDS_FLT = 0b

VDS_FLT_MODE = 0b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Latched:
CLR_FLT

DIS_VDS_FLT = 0b

VDS_FLT_MODE = 1b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Retry:
tLCK_RETRY
VSENSE overcurrent
(SEN_OCP)VSENSE overcurrent
(SEN_OCP)		 VSP > VSENSE_LVL

DIS_SNS_FLT = 0b

SNS_FLT_MODE = 0b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Latched:
CLR_FLT

DIS_SNS_FLT = 0b

SNS_FLT_MODE = 1b

 nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Retry:
tLCK_RETRY
3 Motor Lock
(MTR_LCK )		 Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF MTR_LCK_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
MTR_LCK_MODE = 0010b or 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake logic Active Latched:
CLR_FLT
MTR_LCK_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0110b or 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake logic Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
MTR_LCK_MODE = 1001b to 1111b None Active Active No action
Hardware Lock-Detection Current Limit
(HW_LOCK_ILIMIT)
Phase Current > HW_LOCK_ILIMIT HW_LOCK_ILIMIT_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE =0010b or 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake logic Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 0110b or 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake logic Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
HW_LOCK_ILIMIT_MODE = 1001b to 1111b None Active Active No action
ADC based Lock-Detection Current Limit
(LOCK_ILIMIT)
Phase Current > LOCK_ILIMIT LOCK_ILIMIT_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0010b or 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake logic Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0110b or 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake logic Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
LOCK_ILIMIT_MODE = 1001b to 1111b None Active Active No action
IPD Timeout Fault
(IPD_T1_FAULT)		 IPD TIME > 500ms (approx), during IPD current ramp up or ramp down IPD_TIMEOUT_FAULT_EN = 0b - Active Active No action
IPD_TIMEOUT_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
IPD Frequency Fault
(IPD_FREQ_FAULT)		 IPD pulse before the current decay in previous IPD IPD_FREQ_FAULT_EN = 0b - Active Active No action
IPD_FREQ_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Retry:
tLCK_RETRY
MPET Back-EMF Fault
(MPET_BEMF_FAULT)		 Motor Back EMF < STAT_DETECT_THR MPET_CMD = 1 or
MPET_KE = 1		 nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Maximum VPVDD (over-voltage) fault VPVDD > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b MAX_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
MAX_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Automatic:
(VVM < MAX_VM_MOTOR - VM_UV_OV_HYS) V
Minimum VPVDD (under-voltage) fault VPVDD < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b MIN_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Latched:
CLR_FLT
MIN_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Pulled Low 2(MOSFETs in Hi-Z) Active Automatic:
(VVM > MIN_VM_MOTOR + VM_UV_OV_HYS) V
Bus Current Limit IVM > BUS_CURRENT_LIMIT BUS_CURRENT_LIMIT_ENABLE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed/power/current will be restricted to limit DC bus current Active Automatic: Restriction is removed when IVM < BUS_CURRENT_LIMIT
Current Loop Saturation Indication of current loop saturation due to lower VVM SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed/power/current may not reach reference Active Automatic: motor will reach reference operating point upon exiting saturation
Speed/power Loop Saturation Indication of speed/power loop saturation due to lower VVM, lower ILIMIT setting etc., SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed/power may not reach reference Active Automatic: motor will reach reference operating point upon exiting saturation
External Watchdog Fault Time between watchdog tickles > EXT_WD_CONFIG EXT_WD_EN = 1b
EXT_WD_FAULT = 0b		 nFAULT and CONTROLLER_FA ULT_STATUS register Active Active No action
EXT_WD_EN = 1b
EXT_WD_FAULT = 1b		 nFAULT and CONTROLLER_FA ULT_STATUS register Pulled Low 2 Active Latched:
CLR_FLT
Thermal shutdown
(TSD)		 TJ > TTSD OTS_AUTO_RECOVERY = 0b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Latched:
CLR_FLT
OTS_AUTO_RECOVERY = 1b nFAULT and GATE_DRIVER_FAULT_STATUS Register Pulled Low 2 Active Automatic:
TJ < TOTSD – THYS
  1. Disabled: Passive pull down for GLx and semi-active pull down for GHx
  2. Pulled Low: GHx and GLx are actively pulled low by the gate driver
Note: Any fault reporting on nFAULT pin or CONTROLLER_FAULT_STATUS register or GATE_DRIVER_FAULT_STATUS register can have a latency up to 200 ms.