SLVSH86A December   2023  – June 2024 MCT8314Z

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Secondary Device Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  PWM Control Mode (1x PWM Mode)
        1. 7.3.2.1 Analog Hall Input Configuration
        2. 7.3.2.2 Digital Hall Input Configuration
        3. 7.3.2.3 Asynchronous Modulation
        4. 7.3.2.4 Synchronous Modulation
        5. 7.3.2.5 Motor Operation
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Seven Level Input Pin
      10. 7.3.10 Automatic Synchronous Rectification Mode (ASR Mode)
      11. 7.3.11 Cycle-by-Cycle Current Limit
        1. 7.3.11.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      12. 7.3.12 Hall Comparators (Analog Hall Inputs)
      13. 7.3.13 Advance Angle
      14. 7.3.14 FG Signal
      15. 7.3.15 Protections
        1. 7.3.15.1 VM Supply Undervoltage Lockout (NPOR)
        2. 7.3.15.2 AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.15.3 VCP Charge Pump Undervoltage Lockout (CPUV)
        4. 7.3.15.4 Overvoltage Protections (OVP)
        5. 7.3.15.5 Overcurrent Protection (OCP)
          1. 7.3.15.5.1 OCP Latched Shutdown (OCP_MODE = 00b or MCT8314ZH)
          2. 7.3.15.5.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.15.5.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.15.5.4 OCP Disabled (OCP_MODE = 11b)
        6. 7.3.15.6 Motor Lock (MTR_LOCK)
          1. 7.3.15.6.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
          2. 7.3.15.6.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b or MCT8314ZH)
          3. 7.3.15.6.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
          4. 7.3.15.6.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
        7. 7.3.15.7 Thermal Warning (OTW)
        8. 7.3.15.8 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 STATUS Registers
    2. 8.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Hall Sensor Configuration and Connection
      1. 9.2.1 Typical Configuration
      2. 9.2.2 Open Drain Configuration
      3. 9.2.3 Series Configuration
      4. 9.2.4 Parallel Configuration
    3. 9.3 Typical Applications
      1. 9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit
        1. 9.3.1.1 Detailed Design Procedure
          1. 9.3.1.1.1 Motor Voltage
          2. 9.3.1.1.2 Using Automatic Synchronous Rectification Mode (ASR Mode)
          3. 9.3.1.1.3 Power Dissipation and Junction Temperature Losses
        2. 9.3.1.2 Application Curves
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Considerations
        1. 9.5.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

MCT8314Z MCT8314ZS24-Pin VQFN With Exposed Thermal PadTop ViewFigure 5-1 MCT8314ZS24-Pin VQFN With Exposed Thermal PadTop View
MCT8314Z MCT8314ZH24-Pin VQFN With Exposed Thermal PadTop ViewFigure 5-2 MCT8314ZH24-Pin VQFN With Exposed Thermal PadTop View
Table 5-1 Pin Functions
PIN 24-pin Package TYPE(1) DESCRIPTION
NAME MCT8314ZS MCT8314ZH
ADVANCE — 1 I Advance angle level setting. This pin is a 7-level input pin set by an external resistor.
AGND 16 16 GND Device analog ground. Refer Layout Guidelines for connections recommendation.
AVDD 15 15 PWR O 5.0-V internal regulator output. Connect an X5R or X7R, 2.2-µF, 16-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30 mA externally.
BRAKE 4 4 I High → Brake the motor when High by turning all low side MOSFETs ON
Low → normal operation
CP 7 7 PWR O Charge pump output. Connect a X5R or X7R, 0.22-µF, 16-V ceramic capacitor between the CP and VM pins.
DIR — 2 I Direction pin for setting the direction of the motor rotation to clockwise or counterclockwise.
FG 6 6 O Motor Speed indicator output. Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. It can be set to different division factor of Hall signals (see FG Signal)

FGSEL/

LOCK_DET_TIME

 — 24 I Electrical frequency generation output mode and Motor lock detection time settings. This pin is a 7-level input pin set by an external resistor.
HNA 18 18 I Phase A hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs.
HNB 20 20 I Phase B hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs.
HNC 22 22 I Phase C hall element negative input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs.
HPA 17 17 I Phase A hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs.
HPB 19 19 I Phase B hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs.
HPC 21 21 I Phase C hall element positive input. Noise filter capacitors may be desirable, connected between the positive and negative hall inputs.
ILIM 3 3 I Set the threshold for phase current used in cycle by cycle current limit.
MODE — 23 I PWM input mode setting. This pin is a 7-level input pin set by an external resistor.
nFAULT 13 13 O Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8V to 5.0V. Tie nFAULT to GND if not used.
nSCS 2 — I Serial chip select. A logic low on this pin enables serial interface communication.
nSLEEP 14 14 I Driver nSLEEP. When this pin is logic low, the device goes into a low-power sleep mode. An 20 to 40-µs low pulse can be used to reset fault conditions without entering sleep mode.
OUTA 10 10 PWR O Half bridge output A
OUTB 11 11 PWR O Half bridge output B
OUTC 12 12 PWR O Half bridge output C
PGND 9 9 GND Device power ground. Refer Layout Guidelines for connections recommendation.
PWM 5 5 I PWM input for motor control. Set the duty cycle and switching frequency of the phase voltage of the motor.
SCLK 1 — I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices).
SDI 24 — I Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SDO 23 — O Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices).
VM 8 8 PWR I Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1-µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
Thermal pad GND Must be connected to analog ground.
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect