SLVSH86A December 2023 – June 2024 MCT8314Z
PRODUCTION DATA
The MCT8314Z family of devices is protected against VM undervoltage, charge pump undervoltage, and overcurrent events. Table 7-7 summarizes various faults details.
FAULT | CONDITION | CONFIGURATION | REPORT | H-BRIDGE | LOGIC | RECOVERY |
---|---|---|---|---|---|---|
VM undervoltage (NPOR) | VVM < VUVLO | Device default | — | Hi-Z | Disabled | Automatic: VVM > VUVLO_R CLR_FLT, nSLEEP Reset Pulse (NPOR bit) |
AVDD undervoltage (NPOR) | VAVDD < VAVDD_UV | Device default | — | Hi-Z | Disabled | Automatic: VAVDD > VAVDD_UV_R CLR_FLT, nSLEEP Reset Pulse (NPOR bit) |
Charge pump undervoltage (VCP_UV) | VCP < VCPUV | Device default | nFAULT | Hi-Z | Active | Automatic: VVCP > VCPUV CLR_FLT, nSLEEP Reset Pulse (VCP_UV bit) |
Overvoltage
Protection (OVP) | VVM > VOVP | OVP_EN = 0b | None | Active | Active | No action (OVP Disabled) |
OVP_EN = 1b, HW device default | FAULT | Hi-Z | Active | Automatic: VVM < VOVP CLR_FLT, nSLEEP Reset Pulse (OVP bit) | ||
Overcurrent Protection (OCP) | IPHASE > IOCP | OCP_MODE = 00b, HW device default | nFAULT | Hi-Z | Active | Latched: CLR_FLT, nSLEEP Reset Pulse (OCP bits) |
OCP_MODE = 01b | nFAULT | Hi-Z | Active | Retry: tRETRY | ||
OCP_MODE = 10b | nFAULT | Active | Active | Automatic: CLR_FLT, nSLEEP Reset Pulse (OCP bits) | ||
OCP_MODE = 11b | None | Active | Active | No action | ||
SPI Error (SPI_FLT) | SCLK fault and ADDR fault | SPI_FLT_REP = 0b | nFAULT | Active | Active | Automatic: CLR_FLT, nSLEEP Reset Pulse (SPI_FLT bit) |
SPI_FLT_REP = 1b | None | Active | Active | No action | ||
OTP Error (OTP_ERR) | OTP reading is erroneous | Device default | nFAULT | Hi-Z | Active | Latched: Power Cycle, nSLEEP Reset Pulse |
Motor
Lock (MTR_LOCK) |
No Hall Signals > tMTR_LOCK_TDET | MTR_LOCK_MODE = 00b | nFAULT | Hi-Z | Active | Latched: CLR_FLT, nSLEEP Pulse (MTR_LOCK bit) |
MTR_LOCK_MODE = 01b, HW device default | nFAULT | Hi-Z | Active | Retry: tMTR_LOCK_RETRY |
||
MTR_LOCK_MODE = 10b | nFAULT | Active | Active | Automatic: CLR_FLT, nSLEEP Reset Pulse (OCP bits) |
||
MTR_LOCK_MODE = 11b | None | Active | Active | No action | ||
Thermal warning (OTW) | TJ > TOTW | OTW_REP = 0b | None | Active | Active | No action |
OTW_REP = 1b, HW device default | nFAULT | Active | Active | Automatic: TJ < TOTW – TOTW_HYS CLR_FLT, nSLEEP Pulse (OTW bit) | ||
Thermal shutdown (OTSD_FET) | TJ > TTSD_FET | Device default | nFAULT | Hi-Z | Active | Automatic: TJ < TTSD_FET – TTSD_FET_HYS CLR_FLT, nSLEEP Pulse (OTS bit) |