SLVSH86A December   2023  – June 2024 MCT8314Z

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Secondary Device Mode Timings
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  PWM Control Mode (1x PWM Mode)
        1. 7.3.2.1 Analog Hall Input Configuration
        2. 7.3.2.2 Digital Hall Input Configuration
        3. 7.3.2.3 Asynchronous Modulation
        4. 7.3.2.4 Synchronous Modulation
        5. 7.3.2.5 Motor Operation
      3. 7.3.3  Device Interface Modes
        1. 7.3.3.1 Serial Peripheral Interface (SPI)
        2. 7.3.3.2 Hardware Interface
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Pin Diagrams
        1. 7.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 7.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 7.3.9.3 Open Drain Pin
        4. 7.3.9.4 Push Pull Pin
        5. 7.3.9.5 Seven Level Input Pin
      10. 7.3.10 Automatic Synchronous Rectification Mode (ASR Mode)
      11. 7.3.11 Cycle-by-Cycle Current Limit
        1. 7.3.11.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      12. 7.3.12 Hall Comparators (Analog Hall Inputs)
      13. 7.3.13 Advance Angle
      14. 7.3.14 FG Signal
      15. 7.3.15 Protections
        1. 7.3.15.1 VM Supply Undervoltage Lockout (NPOR)
        2. 7.3.15.2 AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.15.3 VCP Charge Pump Undervoltage Lockout (CPUV)
        4. 7.3.15.4 Overvoltage Protections (OVP)
        5. 7.3.15.5 Overcurrent Protection (OCP)
          1. 7.3.15.5.1 OCP Latched Shutdown (OCP_MODE = 00b or MCT8314ZH)
          2. 7.3.15.5.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.15.5.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.15.5.4 OCP Disabled (OCP_MODE = 11b)
        6. 7.3.15.6 Motor Lock (MTR_LOCK)
          1. 7.3.15.6.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
          2. 7.3.15.6.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b or MCT8314ZH)
          3. 7.3.15.6.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
          4. 7.3.15.6.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
        7. 7.3.15.7 Thermal Warning (OTW)
        8. 7.3.15.8 Thermal Shutdown (OTS)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Operating Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
    5. 7.5 SPI Communication
      1. 7.5.1 Programming
        1. 7.5.1.1 SPI Format
  9. 8 Register Map
    1. 8.1 STATUS Registers
    2. 8.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Hall Sensor Configuration and Connection
      1. 9.2.1 Typical Configuration
      2. 9.2.2 Open Drain Configuration
      3. 9.2.3 Series Configuration
      4. 9.2.4 Parallel Configuration
    3. 9.3 Typical Applications
      1. 9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit
        1. 9.3.1.1 Detailed Design Procedure
          1. 9.3.1.1.1 Motor Voltage
          2. 9.3.1.1.2 Using Automatic Synchronous Rectification Mode (ASR Mode)
          3. 9.3.1.1.3 Power Dissipation and Junction Temperature Losses
        2. 9.3.1.2 Application Curves
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Considerations
        1. 9.5.3.1 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVMQ VM sleep mode current VVM > 6 V, nSLEEP = 0, TA = 25 °C 1.5 2.5 µA
nSLEEP = 0 1.5 5 µA
IVMS VM standby mode current nSLEEP = 1, PWM = BRAKE = 0, SPI = 'OFF' 6.8 10 mA
VVM > 6 V, nSLEEP = 1, PWM = BRAKE = 0, SPI = 'OFF', TA = 25 °C 6.8 8 mA
IVM VM operating mode current VVM > 6 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C 8 9 mA
VVM > 6 V, nSLEEP = 1, fPWM = 100 kHz, TA = 25 °C 9 10 mA
 nSLEEP =1, fPWM = 25 kHz 9 11 mA
nSLEEP =1, fPWM = 100 kHz 9 11 mA
VAVDD Analog regulator voltage VVM > 6 V, 0 mA ≤ IAVDD ≤ 30 mA 4.7 5 5.3 V
IAVDD External analog regulator load 30 mA
CAVDD Capacitance for AVDD(1) External load: 0mA ≤IAVDD ≤ 30 mA 0.7 2.2 2.64 uF
VCP Charge pump regulator voltage VCP with respect to VM 3.5 4.7 5.2 V
CCP Charge pump capacitance (1) Capacitance between CP and VM 80 220 330 nF
tWAKE Wakeup time VVM > VUVLO, nSLEEP = 1 to outputs ready and nFAULT released 3.5 5 ms
tSLEEP Time to enter sleep mode nSLEEP = 0 period to enter sleep mode 120 µs
tRST Reset Pulse time nSLEEP = 0 period to reset faults 20 40 µs
LOGIC-LEVEL INPUTS (PWM, BRAKE, DIR, nSLEEP, SCLK, SDI, nSCS)
VIL Input logic low voltage 0 0.6 V
VIH Input logic high voltage Other Pins 1.5 5.5 V
nSLEEP 1.6 5.5 V
VHYS Input logic hysteresis Other Pins 150 250 420 mV
nSLEEP 95 300 420 mV
IIL Input logic low current VPIN (Pin Voltage) = 0 V –1 1 µA
IIH Input logic high current nSCS, VnSCS (Pin Voltage) = 5 V, VM < 6 V –1 1 µA
nSCS, VnSCS (Pin Voltage) = 5 V, VM ≥ 6 V –1 1 µA
nSLEEP, VnSLEEP (Pin Voltage) = 5 V 10 30 µA
Other pins, VPIN (Pin Voltage) = 5 V 25 75 µA
RPD Input pulldown resistance nSLEEP 150 225 300 kΩ
Other pins 70 100 130 kΩ
CID Input capacitance 30 pF
SEVEN-LEVEL INPUTS (ADVANCE, MODE, FGSEL/LOCK_DET_TIME)
VL1 Input mode 1 voltage Tied to AGND 0 0.09*VAVDD V
VL2 Input mode 2 voltage 22 kΩ ± 5% to AGND 0.12*VAVDD 0.15*VAVDD 0.2*VAVDD V
VL3 Input mode 3 voltage 100 kΩ ± 5% to AGND 0.27*VAVDD 0.33*VAVDD 0.4*VAVDD V
VL4 Input mode 4 voltage Hi-Z 0.45*VAVDD 0.5*VAVDD 0.55*VAVDD V
VL5 Input mode 5 voltage 100 kΩ ± 5% to AVDD 0.6*VAVDD 0.66*VAVDD 0.73*VAVDD V
VL6 Input mode 6 voltage 22 kΩ ± 5% to AVDD 0.77*VAVDD 0.85*VAVDD 0.9*VAVDD V
VL7 Input mode 7 voltage Tied to AVDD 0.94*VAVDD VAVDD V
RPU Input pullup resistance To AVDD 80 100 120 kΩ
RPD Input pulldown resistance To AGND 80 100 120 kΩ
OPEN-DRAIN OUTPUTS (FG, SDO)
VOL Output logic low voltage IOD = 5 mA 0.4 V
IOH Output logic high current VOD = 5 V –1 1 µA
COD Output capacitance 30 pF
PUSH-PULL OUTPUTS (SDO)
VOL Output logic low voltage IOP = 5 mA 0 0.4 V
VOH Output logic high voltage IOP = 5 mA 2.2 5.5 V
IOL Output logic low leakage current VOP = 0 V –1 1 µA
IOH Output logic high leakage current VOP = 5 V –1 1 µA
COD Output capacitance 30 pF
DRIVER OUTPUTS
RDS(ON) Total MOSFET on resistance (High-side + Low-side) VVM > 6 V, IOUT = 1 A, TA = 25°C 575 630 mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C 596 660 mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C 868 960 mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C 889 972 mΩ
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %)
 		 VVM = 24 V, 50 mA ≤ IOUT ≤ 1.5 A 100 200 320 V/us
Phase pin slew rate switching high to low (Falling from 80 % to 20 %)
 		 VVM = 24 V, 50 mA ≤ IOUT ≤ 1.5 A 100 200 320 V/us
ILEAK Leakage current into OUTx VOUTx = VVM, nSLEEP = 1 -5 0 mA
Leakage current into OUTx  VOUTx = 0 V, nSLEEP = 1 1 µA
tDEAD Output dead time (high to low / low to high) VVM = 24 V, HS driver OFF to LS driver ON 500 750 ns
tPD Propagation delay (high-side / low-side ON/OFF) VVM = 24 V, 50 mA ≤ IOUT ≤ 1.5 A, PWM pin transition to OUTx transisition 650 1050 ns
tMIN_PULSE Minimum input pulse width for valid output pulse 600 ns
HALL COMPARATORS
VICM Input Common Mode Voltage (Hall) 0.5 AVDD – 1.2 V
VHYS_HALL Voltage hysteresis (SPI Device) HALL_HYS = 0 1.5 5 10 mV
HALL_HYS = 1 35 50 80 mV
Voltage hysteresis (HW Device) 1.5 5 10 mV
ΔVHYS_HALL Hall comparator hysteresis difference Between Hall A, Hall B and Hall C comparator –8 8 mV
II Input leakage current HPx = HNx = 0 V –1 1 μA
tHDG Hall deglitch time 0.6 1.15 1.7 μs
tHEDG Hall Enable deglitch time During power up 1.4 μs
CYCLE-BY-CYCLE CURRENT LIMIT
ILIMIT Current limit RILIMIT = 18 kΩ 0.46 0.5 0.59 A
RILIMIT = 9 kΩ 0.91 1 1.13 A
RILIMIT = 6 kΩ 1.35 1.5 1.66 A
tBLANK Cycle by cycle current limit blank time 5.0 µs
ADVANCE ANGLE
θADV Advance Angle Setting
(SPI Device)		 ADVANCE_LVL = 000 b 0 1 °
ADVANCE_LVL = 001 b 3 4 5 °
ADVANCE_LVL = 010 b 6 7 8
°
ADVANCE_LVL = 011 b 10 11 12
°
ADVANCE_LVL = 100 b 13.5 15 16.5
°
ADVANCE_LVL = 101 b 18 20 22
°
ADVANCE_LVL = 110 b 22.5 25 27.5
°
ADVANCE_LVL = 111 b 27 30 33
°
θADV Advance Angle Setting
(HW Device)		 ADVANCE pin tied to AGND 0 1
°
ADVANCE pin tied to 22 kΩ ± 5% to AGND 3 4 5
°
ADVANCE pin tied to 100 kΩ ± 5% to AGND 10 11 12
°
ADVANCE pin tied to Hi-Z 13.5 15 16.5
°
ADVANCE pin tied to 100 kΩ ± 5% to AVDD 18 20 22
°
ADVANCE pin tied to 22 kΩ ± 5% to AVDD 22.5 25 27.5
°
ADVANCE pin tied to Tied to AVDD 27 30 33
°
PROTECTION CIRCUITS
VUVLO VM supply undervoltage lockout (UVLO) VM falling 4.25 4.35 4.48 V
VM rising 4.42 4.6 4.75 V
VUVLO_HYS VM supply undervoltage lockout hysteresis Rising to falling threshold 130 210 260 mV
tUVLO VM supply undervoltage deglitch time 3 5 7 µs
VOVP Supply overvoltage protection (OVP)
(SPI Device)		 Supply rising, OVP_EN = 1, OVP_SEL = 0 32.5 34 35 V
Supply falling, OVP_EN = 1, OVP_SEL = 0 31.8 33 34.3 V
Supply rising, OVP_EN = 1, OVP_SEL = 1 20 22 23 V
Supply falling, OVP_EN = 1, OVP_SEL = 1 19 21 22 V
VOVP_HYS Supply overvoltage protection hysteresis
(SPI Device)		 Rising to falling threshold, OVP_SEL = 1 0.9 1 1.1 V
Rising to falling threshold, OVP_SEL = 0 0.65 0.8 0.9 V
VOVP Supply overvoltage protection (OVP)
(HW Device)		 Supply rising 32.5 34 35 V
Supply falling 31.8 33 34.3 V
VOVP_HYS Supply overvoltage protection hysteresis
(HW Device)		 Rising to falling threshold 0.65 0.8 0.9 V
tOVP Supply overvoltage deglitch time 2.5 5 7 µs
VCPUV Charge pump undervoltage lockout (above VM) Supply rising 2.2 2.5 2.8 V
Supply falling 2.1 2.4 2.7 V
VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 75 100 140 mV
VAVDD_UV Analog regulator undervoltage lockout Supply falling 3 3.1 3.3 V
Supply rising 3.2 3.3 3.47 V
VAVDD_UV_HYS Analog regulator undervoltage lockout hysteresis Rising to falling threshold 150 200 255 mV
IOCP Overcurrent protection trip point 2.25 3.25 4.25 A
tOCP Overcurrent protection deglitch time
(SPI Device)		 OCP_DEG = 00b 0.02 0.2 0.4 µs
OCP_DEG = 01b 0.2 0.6 1.2 µs
OCP_DEG = 10b 0.5 1.2 1.8 µs
OCP_DEG = 11b 0.9 1.6 2.5 µs
Overcurrent protection deglitch time
(HW Device)		 0.2 0.6 1.2 µs
tRETRY Overcurrent protection retry time
(SPI Device)		 OCP_RETRY = 0 4 5 6 ms
OCP_RETRY = 1 425 500 575 ms
tPWM_LOW PWM low time required for motor lock detection 200 ms
tMTR_LOCK Motor lock detection time
(SPI Device)		 MOTOR_LOCK_TDET = 00b 270 300 330 ms
MOTOR_LOCK_TDET = 01b 450 500 550 ms
MOTOR_LOCK_TDET = 10b 900 1000 1100 ms
MOTOR_LOCK_TDET = 11b 4500 5000 5500 ms
tMTR_LOCK Motor lock detection time
(HW Device)		 FGSEL/LOCK_DET_TIME pin tied to AGND or tied to 100 kΩ ± 5% to AVDD 270 300 330 ms
FGSEL/LOCK_DET_TIME pin tied to 22 kΩ ± 5% to AGND or tied to 22 kΩ ± 5% to AVDD 450 500 550 ms
FGSEL/LOCK_DET_TIME pin tied to 100 kΩ ± 5% to AGND or tied to AVDD 900 1000 1100 ms
FGSEL/LOCK_DET_TIME pin floating (HiZ) 4500 5000 5500 ms
tMTR_LOCK_RETRY Motor lock retry time
(SPI Device)		 MOTOR_LOCK_RETRY = 0b 450 500 550 ms
MOTOR_LOCK_RETRY = 1b 4500 5000 5500 ms
tMTR_LOCK_RETRY Motor lock retry time
(HW Device)		 450 500 550 ms
TOTW_LDO Thermal shutdown temperature  Die temperature (TJ) 147 171 184 °C
TOTW_LDO_HYS Thermal shutdown hysteresis  Die temperature (TJ) 15 20 25 °C
TOTW_FET Thermal warning temperature Die temperature (TJ) 132 145 158 °C
TOTW_FET_HYS Thermal warning hysteresis Die temperature (TJ) 15 20 25 °C
TTSD_FET Thermal shutdown temperature (FET) Die temperature (TJ) 150 165 178 °C
TTSD_FET_HYS Thermal shutdown hysteresis (FET) Die temperature (TJ) 17 18 19 °C
(1) Effective capacitance including variations due to DC bias, temperature, manufacturing tolerance, etc.