SLVSH86A
December 2023 – June 2024
MCT8314Z
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
SPI Timing Requirements
6.7
SPI Secondary Device Mode Timings
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Output Stage
7.3.2
PWM Control Mode (1x PWM Mode)
7.3.2.1
Analog Hall Input Configuration
7.3.2.2
Digital Hall Input Configuration
7.3.2.3
Asynchronous Modulation
7.3.2.4
Synchronous Modulation
7.3.2.5
Motor Operation
7.3.3
Device Interface Modes
7.3.3.1
Serial Peripheral Interface (SPI)
7.3.3.2
Hardware Interface
7.3.4
AVDD Linear Voltage Regulator
7.3.5
Charge Pump
7.3.6
Slew Rate
7.3.7
Cross Conduction (Dead Time)
7.3.8
Propagation Delay
7.3.9
Pin Diagrams
7.3.9.1
Logic Level Input Pin (Internal Pulldown)
7.3.9.2
Logic Level Input Pin (Internal Pullup)
7.3.9.3
Open Drain Pin
7.3.9.4
Push Pull Pin
7.3.9.5
Seven Level Input Pin
7.3.10
Automatic Synchronous Rectification Mode (ASR Mode)
7.3.11
Cycle-by-Cycle Current Limit
7.3.11.1
Cycle by Cycle Current Limit with 100% Duty Cycle Input
7.3.12
Hall Comparators (Analog Hall Inputs)
7.3.13
Advance Angle
7.3.14
FG Signal
7.3.15
Protections
7.3.15.1
VM Supply Undervoltage Lockout (NPOR)
7.3.15.2
AVDD Undervoltage Lockout (AVDD_UV)
7.3.15.3
VCP Charge Pump Undervoltage Lockout (CPUV)
7.3.15.4
Overvoltage Protections (OVP)
7.3.15.5
Overcurrent Protection (OCP)
7.3.15.5.1
OCP Latched Shutdown (OCP_MODE = 00b or MCT8314ZH)
7.3.15.5.2
OCP Automatic Retry (OCP_MODE = 01b)
7.3.15.5.3
OCP Report Only (OCP_MODE = 10b)
7.3.15.5.4
OCP Disabled (OCP_MODE = 11b)
7.3.15.6
Motor Lock (MTR_LOCK)
7.3.15.6.1
MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
7.3.15.6.2
MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b or MCT8314ZH)
7.3.15.6.3
MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
7.3.15.6.4
MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
7.3.15.7
Thermal Warning (OTW)
7.3.15.8
Thermal Shutdown (OTS)
7.4
Device Functional Modes
7.4.1
Functional Modes
7.4.1.1
Sleep Mode
7.4.1.2
Operating Mode
7.4.1.3
Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
7.5
SPI Communication
7.5.1
Programming
7.5.1.1
SPI Format
8
Register Map
8.1
STATUS Registers
8.2
CONTROL Registers
9
Application and Implementation
9.1
Application Information
9.2
Hall Sensor Configuration and Connection
9.2.1
Typical Configuration
9.2.2
Open Drain Configuration
9.2.3
Series Configuration
9.2.4
Parallel Configuration
9.3
Typical Applications
9.3.1
Three-Phase Brushless-DC Motor Control With Current Limit
9.3.1.1
Detailed Design Procedure
9.3.1.1.1
Motor Voltage
9.3.1.1.2
Using Automatic Synchronous Rectification Mode (ASR Mode)
9.3.1.1.3
Power Dissipation and Junction Temperature Losses
9.3.1.2
Application Curves
9.4
Power Supply Recommendations
9.4.1
Bulk Capacitance
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
9.5.3
Thermal Considerations
9.5.3.1
Power Dissipation
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
RRW|24
MPQF657A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsh86a_oa
6.2
ESD Ratings
VALUE
UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
±2000
V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002
(2)
±500
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.