SLLSFP7A december 2022 – april 2023 MCT8315A
PRODUCTION DATA
Table 7-29 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 7-29 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
A4h | PIN_CONFIG1 | Hardware pin configuration | PIN_CONFIG1 Register (Offset = A4h) [Reset = 00000000h] |
A6h | PIN_CONFIG2 | Hardware pin configuration | PIN_CONFIG2 Register (Offset = A6h) [Reset = 00000000h] |
A8h | DEVICE_CONFIG | Device configuration | DEVICE_CONFIG Register (Offset = A8h) [Reset = 00000000h] |
Complex bit access types are encoded to fit into small table cells. Table 7-30 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
PIN_CONFIG1 is shown in Figure 7-71 and described in Table 7-31.
Return to the Summary Table.
Register to configure hardware pins
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PARITY | DACOUT1_VAR_ADDR | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DACOUT1_VAR_ADDR | DACOUT2_VAR_ADDR | ||||||
R/W-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DACOUT2_VAR_ADDR | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DACOUT2_VAR_ADDR | BRAKE_INPUT | DIR_INPUT | SPD_CTRL_MODE | ALARM_PIN_EN | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R/W | 0h | Parity bit |
30-19 | DACOUT1_VAR_ADDR | R/W | 0h | 12-bit address of variable to be monitored |
18-7 | DACOUT2_VAR_ADDR | R/W | 0h | 12-bit address of variable to be monitored |
6-5 | BRAKE_INPUT | R/W | 0h | Brake input configuration
0h = Hardware Pin BRAKE 1h = Overwrite Hardware pin with Active Brake 2h = Overwrite Hardware pin with brake functionality disabled 3h = Reserved |
4-3 | DIR_INPUT | R/W | 0h | Direction input configuration
0h = Hardware Pin DIR 1h = Overwrite Hardware pin with clockwise rotation OUTA-OUTB-OUTC 3h = Reserved |
2-1 | SPD_CTRL_MODE | R/W | 0h | Speed input configuration
0h = Analog mode 1h = PWM mode 2h = 0x2 3h = Frequency mode |
0 | ALARM_PIN_EN | R/W | 0h | Alarm Pin GPIO configuration
0h = Disabled (Hi-Z) 1h = Enabled |
PIN_CONFIG2 is shown in Figure 7-72 and described in Table 7-32.
Return to the Summary Table.
Register to configure hardware pins
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PARITY | DAC_SOX_CONFIG | RESERVED | DAC_CONFIG | I2C_TARGET_ADDR | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
I2C_TARGET_ADDR | SLEEP_TIME | EXT_WD_EN | EXT_WD_INPUT | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EXT_WD_FAULT | EXT_WD_FREQ | FG_PIN_FAULT_CONFIG | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R/W | 0h | Parity bit |
30-29 | DAC_SOX_CONFIG | R/W | 0h | Pin 36 configuration
0h = DACOUT2 1h = SOA 2h = SOB 3h = SOC |
28 | RESERVED | R/W | 0h | Reserved |
27 | DAC_CONFIG | R/W | 0h | Pin 37 and pin 38 configuration
0h = Reserved 1h = Pin 37 as DACOUT2 and pin 38 as DACOUT1 |
26-20 | I2C_TARGET_ADDR | R/W | 0h | I2C target address |
19-18 | SLEEP_TIME | R/W | 0h | Sleep Time
0h = Check low for 50 µs 1h = Check low for 200 µs 2h = Check low for 20 ms 3h = Check low for 200 ms |
17 | EXT_WD_EN | R/W | 0h | Enable external watchdog
0h = Disable 1h = Enable |
16 | EXT_WD_INPUT | R/W | 0h | External watchdog source
0h = I2C 1h = GPIO |
15 | EXT_WD_FAULT | R/W | 0h | External watchdog fault mode
0h = Report only 1h = Latched fault with Hi-Z outputs |
14-13 | EXT_WD_FREQ | R/W | 0h | External watchdog frequency
0h = 10Hz 1h = 5Hz 2h = 2Hz 3h = 1Hz |
12-11 | FG_PIN_FAULT_CONFIG | R/W | 0h | Fault on FG Pin Configuration
0h = FG continues to toggle till motor stops 1h = FG in Hi-Z state, pulled up externally 2h = FG pulled Low 3h = Reserved |
10-0 | RESERVED | R/W | 0h | Reserved |
DEVICE_CONFIG is shown in Figure 7-73 and described in Table 7-33.
Return to the Summary Table.
Register to configure device
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PARITY | INPUT_MAX_FREQUENCY | ||||||
R/W-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
INPUT_MAX_FREQUENCY | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | SSM_CONFIG | RESERVED | DEV_MODE | SPD_PWM_RANGE_SELECT | CLK_SEL | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_CLK_EN | EXT_CLK_CONFIG | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R/W | 0h | Parity bit |
30-16 | INPUT_MAX_FREQUENCY | R/W | 0h | Maximum frequency (in Hz) for frequency based speed input |
15 | RESERVED | R/W | 0h | Reserved |
14 | SSM_CONFIG | R/W | 0h | SSM enable
0h = Enable 1h = Disable |
13-12 | RESERVED | R/W | 0h | Reserved |
11 | DEV_MODE | R/W | 0h | Device mode select
0h = Standby mode 1h = Sleep mode |
10 | SPD_PWM_RANGE_SELECT | R/W | 0h | PWM frequency range select
0h = 325 Hz to 100 kHz speed PWM input 1h = 10 Hz to 325 Hz speed PWM input |
9-8 | CLK_SEL | R/W | 0h | Clock source
0h = Internal Oscillator 1h = Reserved 2h = Reserved 3h = External Clock input |
7 | RESERVED | R/W | 0h | Reserved |
6 | EXT_CLK_EN | R/W | 0h | External clock enable
0h = Disable 1h = Enable |
5-3 | EXT_CLK_CONFIG | R/W | 0h | External clock frequency
0h = 8 kHz 1h = 16 kHz 2h = 32 kHz 3h = 64 kHz 4h = 128 kHz 5h = 256 kHz 6h = 512 kHz 7h = 1024 kHz |
2-0 | RESERVED | R/W | 0h | Reserved |