SLLSFP7A december   2022  – april 2023 MCT8315A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Under Voltage Protection
        7. 7.3.3.7 Buck Over Current Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Speed Control
        1. 7.3.8.1 Analog Mode Speed Control
        2. 7.3.8.2 PWM Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency Mode Speed Control
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 120o Commutation
          1. 7.3.11.1.1 High-Side Modulation
          2. 7.3.11.1.2 Low-Side Modulation
          3. 7.3.11.1.3 Mixed Modulation
        2. 7.3.11.2 Variable Commutation
        3. 7.3.11.3 Lead Angle Control
        4. 7.3.11.4 Closed loop accelerate
      12. 7.3.12 Speed Loop
      13. 7.3.13 Input Power Regulation
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Fast Start-up (< 50 ms)
        1. 7.3.16.1 BEMF Threshold
        2. 7.3.16.2 Dynamic Degauss
      17. 7.3.17 Fast Deceleration
      18. 7.3.18 Active Demagnetization
        1. 7.3.18.1 Active Demagnetization in action
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 Protections
        1. 7.3.21.1  VM Supply Undervoltage Lockout
        2. 7.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.21.5  Overvoltage Protection (OVP)
        6. 7.3.21.6  Overcurrent Protection (OCP)
          1. 7.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.21.7  Buck Overcurrent Protection
        8. 7.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.21.10 Thermal Warning (OTW)
        11. 7.3.21.11 Thermal Shutdown (TSD)
        12. 7.3.21.12 Motor Lock (MTR_LCK)
          1. 7.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.21.13 Motor Lock Detection
          1. 7.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.21.14 SW VM Undervoltage Protection
        15. 7.3.21.15 SW VM Overvoltage Protection
        16. 7.3.21.16 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 120o and variable commutation
        3. 8.2.1.3 Faster startup time
        4. 8.2.1.4 Setting the BEMF threshold
        5. 8.2.1.5 Maximum speed
        6. 8.2.1.6 Faster deceleration
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 35 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 24 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVMQ VM sleep mode current VVM > 6 V, VSPEED = 0, TA = 25 °C 3 5 µA
VSPEED = 0, TA = 125 °C 3.5 7 µA
IVMS VM standby mode current VVM ≥ 12 V, Standby Mode, DRVOFF = High, TA = 25 °C, LBK = 47 uH, CBK = 22 µF  8 16 mA
VVM > 6 V, Standby Mode, DRVOFF = High, TA = 25 °C, RBK = 22 Ω, CBK = 22 µF 25 29 mA
VVM ≥ 12 V, Standby Mode, DRVOFF = High, LBK = 47 uH, CBK = 22 µF  8 16.5 mA
VVM > 6 V, Standby Mode, DRVOFF = High, RBK = 22 Ω, CBK = 22 µF 25 29 mA
IVM VM operating mode current VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), TA = 25 °C, LBK = 47 uH, CBK = 22 µF, No Motor Connected 11 18 mA
VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), TA = 25 °C, RBK = 22 Ω, CBK = 22 µF, No Motor Connected 27 30.5 mA
VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), LBK = 47 uH, CBK = 22 µF, No Motor Connected 11 17 mA
VVM > 6 V, VSPEED > VEX_SL, PWM_FREQ_OUT = 10000b (25 kHz), RBK = 22 Ω, CBK = 22 µF, No Motor Connected 28 30.5 mA
VAVDD Analog regulator voltage 0 mA ≤ IAVDD ≤ 20 mA 3.125 3.3 3.465 V
IAVDD External analog regulator load 20 mA
VDVDD Digital regulator voltage 1.4 1.55 1.65 V
VVCP Charge pump regulator voltage VCP with respect to VM 4.0 4.7 5.5 V
BUCK REGULATOR
VBK Buck regulator average voltage
(LBK = 47 µH, CBK = 22 µF)
 		 VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V
VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 170 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 170 mA VVM–IBK*(RLBK+2) 1 V
VBK Buck regulator average voltage
(LBK = 22 µH, CBK = 22 µF)
 		 VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 20 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 20 mA VVM–IBK*(RLBK+2)1 V
VBK Buck regulator average voltage
(RBK = 22 Ω, CBK = 22 µF)
 		 VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 00b 3.1 3.3 3.5 V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 01b 4.6 5.0 5.4 V
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 10b 3.7 4.0 4.3 V
VVM > 6.7 V, 0 mA ≤ IBK ≤ 10 mA, BUCK_SEL = 11b 5.2 5.7 6.2 V
VVM < 6.0 V (BUCK_SEL = 00b, 01b, 10b, 11b), 0 mA ≤ IBK ≤ 10 mA VVM–IBK*(RBK+2) V
VBK_RIP Buck regulator ripple voltage VVM > 6 V, 0 mA ≤ IBK ≤ 170 mA, Buck regulator with inductor, LBK = 47 uH, CBK = 22 µF –100 100 mV
VVM > 6 V, 0 mA ≤ IBK ≤ 20 mA, Buck regulator with inductor, LBK = 22 uH, CBK = 22 µF –100 100 mV
VVM > 6 V, 0 mA ≤ IBK ≤ 10 mA, Buck regulator with resistor; RBK = 22 Ω, CBK = 22 µF –100 100 mV
IBK External buck regulator load LBK = 47 uH, CBK = 22 µF, BUCK_PS_DIS = 1b 170 mA
LBK = 47 uH, CBK = 22 µF, BUCK_PS_DIS = 0b 170 – IAVDD mA
LBK = 22 uH, CBK = 22 µF, BUCK_PS_DIS = 1b 20 mA
LBK = 22 uH, CBK = 22 µF, BUCK_PS_DIS = 0b 20 – IAVDD mA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 1b 10 mA
RBK = 22 Ω, CBK = 22 µF, BUCK_PS_DIS = 0b 10 – IAVDD mA
fSW_BK Buck regulator switching frequency Regulation Mode 20 535 kHz
Linear Mode 20 535 kHz
VBK_UV Buck regulator undervoltage lockout
 		 VBK rising, BUCK_SEL = 00b 2.7 2.8 2.95 V
VBK falling, BUCK_SEL = 00b 2.5 2.6 2.7 V
VBK rising, BUCK_SEL = 01b 4.3 4.4 4.55 V
VBK falling, BUCK_SEL = 01b 4.1 4.2 4.36 V
VBK rising, BUCK_SEL = 10b 2.7 2.8 2.95 V
VBK falling, BUCK_SEL = 10b 2.5 2.6 2.7 V
VBK rising, BUCK_SEL = 11b 4.3 4.4 4.55 V
VBK falling, BUCK_SEL = 11b 4.1 4.2 4.36 V
VBK_UV_HYS Buck regulator undervoltage lockout hysteresis Rising to falling threshold, BUCK_SEL = 00b 90 200 400 mV
Rising to falling threshold, BUCK_SEL = 01b 90 200 400 mV
Rising to falling threshold, BUCK_SEL = 10b 90 200 400 mV
Rising to falling threshold, BUCK_SEL =11b 90 200 400 mV
IBK_CL Buck regulator current limit threshold
 		 BUCK_CL = 0b 360 600 910 mA
BUCK_CL = 1b 80 150 250 mA
IBK_OCP Buck regulator over current protection trip point 2 3 4 A
tBK_RETRY Over current protection retry time 0.7 1 1.3 ms
DRIVER OUTPUTS
RDS(ON) Total MOSFET on resistance (High-side + Low-side) VVM > 6 V, IOUT = 1 A, TA = 25°C 240 260 mΩ
VVM < 6 V, IOUT = 1 A, TA = 25°C 250 270 mΩ
VVM > 6 V, IOUT = 1 A, TJ = 150 °C 360 400 mΩ
VVM < 6 V, IOUT = 1 A, TJ = 150 °C 370 415 mΩ
SR Phase pin slew rate switching low to high (Rising from 20 % to 80 %) VVM = 24 V, SLEW_RATE = 00b 13 25 45 V/µs
VVM = 24 V, SLEW_RATE = 01b 30 50 80 V/µs
VVM = 24 V, SLEW_RATE = 10b 80 125 185 V/µs
VVM = 24 V, SLEW_RATE = 11b 130 200 280 V/µs
SR Phase pin slew rate switching high to low (Falling from 80 % to 20 %) VVM = 24 V, SLEW_RATE = 00b 14 25 45 V/µs
VVM = 24 V, SLEW_RATE = 01b 30 50 80 V/µs
VVM = 24 V, SLEW_RATE = 10b 80 125 185 V/µs
VVM = 24 V, SLEW_RATE = 11b 110 200 280 V/µs
tDEAD Output dead time (high to low / low to high) VVM = 24 V, SR = 25 V/µs 1800 3000 ns
VVM = 24 V, SR = 50 V/µs 1100 1400 ns
VVM = 24 V, SR = 125 V/µs 650 850 ns
VVM = 24 V, SR = 200 V/µs 500 550 ns
SPEED INPUT - PWM MODE
ƒPWM PWM input frequency 0.01 100 kHz
ResPWM PWM input resolution fPWM = 0.01 to 0.35 kHz 11 12 13 bits
fPWM = 0.35 to 2 kHz 11 13 14 bits
fPWM = 2 to 3.5 kHz 11 11.5 12 bits
fPWM = 3.5 to 7 kHz 12 13 13.5 bits
fPWM = 7 to 14 kHz 11 12 12.5 bits
fPWM = 14 to 29.2 kHz  10 11.5 12 bits
fPWM = 29.3 to 60 kHz 9 10.5 11 bits
fPWM = 60 to 100 kHz 8 9 10 bits
SPEED INPUT - ANALOG MODE
VANA_FS Analog full-speed voltage 2.95 3 3.05 V
VANA_RES Analog voltage resolution 732 μV
SPEED INPUT - FREQUENCY MODE
ƒPWM_FREQ PWM input frequency range  Duty cycle = 50% 3 32767 Hz
SLEEP MODE
VEN_SL Analog voltage to enter sleep mode SPD_CTRL_MODE = 00b (analog mode) 40 mV
VEX_SL Analog voltage to exit sleep mode SPD_CTRL_MODE = 00b (analog mode) 2.2 V
tDET_ANA Time needed to detect wake up signal on SPEED pin  SPD_CTRL_MODE = 00b (analog mode)
VSPEED > VEX_SL		 0.5 1 1.5 μs
tWAKE Wakeup time from sleep mode VSPEED > VEX_SL to DVDD voltage available, SPD_CTRL_MODE = 00b (analog mode) 3 5 ms
tEX_SL_DR_ANA Time taken to drive motor after exiting from sleep state SPD_CTRL_MODE = 00b (analog mode)
VSPEED > VEX_SL, ISD detection disabled		 30 ms
tDET_PWM Time needed to detect wake up signal on SPEED pin  SPD_CTRL_MODE = 01b (PWM mode), VSPEED > VIH 0.5 1 1.5 μs
tWAKE_PWM Wakeup time from sleep mode VSPEED > VIH to DVDD voltage available, SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode) 3 5 ms
tEX_SL_DR_PWM Time taken to drive motor after wakeup from sleep state SPD_CTRL_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled		 30 ms
tDET_SL_ANA Time needed to detect sleep command, analog mode SPD_CTRL_MODE = 00b (analog mode) VSPEED < VEN_SL, SLEEP_TIME = 00b or 01b 0.5 1 2 ms
SPD_CTRL_MODE = 00b (analog mode) VSPEED < VEN_SL, SLEEP_TIME = 10b 14 20 26 ms
SPD_CTRL_MODE = 00b (analog mode) VSPEED < VEN_SL, SLEEP_TIME = 11b 140 200 260 ms
tDET_SL_PWM Time needed to detect sleep command, PWM or frequency mode SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 00b		 0.035 0.05 0.065 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 01b		 0.14 0.2 0.26 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 10b		 14 20 26 ms
SPD_CTRL_MODE = 01b (PWM mode) or 11b (Frequency mode),
VSPEED < VIL, SLEEP_TIME = 11b		 140 200 260 ms
tEN_SL Time needed to stop driving motor after detecting sleep command VSPEED < VEN_SL (analog mode) or VSPEED < VIL (PWM mode) (and SPEED_CTRL = 0 (I2C mode)) 1 2 ms
STANDBY MODE
tEX_SB_DR_ANA Time taken to drive motor after exiting standby mode, analog mode SPD_CTRL_MODE = 00b (analog mode), VSPEED > VEX_SB, ISD detection disabled 6 ms
tEX_SB_DR_PWM Time taken to drive motor after exiting standby mode, PWM mode SPD_CTRL_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled		 6 ms
tDET_SB_ANA Time needed to detect standby mode, analog mode SPD_CTRL_MODE = 00b (analog mode), VSPEED < VEN_SB 0.5 1 2 ms
tDET_SB_PWM Time needed to detect standby command, PWM/ mode SPD_CTRL_MODE = 01b (PWM mode),
VSPEED < VIL, SLEEP_TIME = 00b		 0.035 0.05 0.065 ms
SPD_CTRL_MODE = 01b (PWM mode), VSPEED < VIL, SLEEP_TIME = 01b 0.14 0.2 0.26 ms
SPD_CTRL_MODE = 01b (PWM mode), VSPEED < VIL, SLEEP_TIME = 10b 14 20 26 ms
SPD_CTRL_MODE = 01b (PWM mode),
VSPEED < VIL, SLEEP_TIME = 11b		 140 200 260 ms
tDET_SB_FREQ Time needed to detect standby mode, Frequency mode SPD_CTRL_MODE = 11b (Frequency mode), VSPEED < VIL 4000 ms
tDET_SB_DIG Time needed to detect standby mode, I2C mode SPD_CTRL_MODE = 10b (I2C mode), SPEED_CTRL = 0b 1 2 ms
tEN_SB Time needed to stop driving motor after detecting standby command All speed input modes 1 2 ms
LOGIC-LEVEL INPUTS (BRAKE, DIR, EXT_CLK, EXT_WD, SPEED)
VIL Input logic low voltage AVDD = 3 to 3.6 V 0.25*AVDD V
VIH Input logic high voltage AVDD = 3 to 3.6 V 0.65*AVDD V
VHYS Input hysteresis 50 500 800 mV
IIL Input logic low current AVDD = 3 to 3.6 V -0.15 0.15 µA
IIH Input logic high current AVDD  = 3 to 3.6 V -0.3 0 µA
RPD_SPEED Input pulldown resistance SPEED pin To GND 0.6 1 1.4 MΩ
OPEN-DRAIN OUTPUTS (nFAULT, FG)
VOL Output logic low voltage IOD = -5 mA 0.4 V
IOZ Output logic high current VOD = 3.3 V 0 0.5 µA
I2C Serial Interface
VI2C_L Input logic low voltage -0.5 0.3*AVDD V
VI2C_H Input logic high voltage 0.7*AVDD 5.5 V
VI2C_HYS Hysteresis  0.05*AVDD V
VI2C_OL Output logic low voltage Open-drain at 2mA sink current  0 0.4 V
II2C_OL Output logic low current VI2C_OL = 0.6V 6 mA
II2C_IL Input current on SDA and SCL -102 102 µA
Ci Capacitance for SDA and SCL 10 pF
tof Output fall time from VI2C_H(min) to VI2C_L(max) Standard Mode 2503 ns
Fast Mode 2503 ns
tSP Pulse width of spikes that must be suppressed by the input filter Fast Mode 0 504 ns
OSCILLATOR
fOSCREF External clock reference EXT_CLK_CONFIG = 000b 8 kHz
EXT_CLK_CONFIG = 001b 16 kHz
EXT_CLK_CONFIG = 010b 32 kHz
EXT_CLK_CONFIG = 011b 64 kHz
EXT_CLK_CONFIG = 100b 128 kHz
EXT_CLK_CONFIG = 101b 256 kHz
EXT_CLK_CONFIG = 110b 512 kHz
EXT_CLK_CONFIG = 111b 1024 kHz
EEPROM
EEProg Programming voltage 1.35 1.5 1.65 V
EERET Retention TA = 25 ℃ 100 Years
TJ = -40 to 150 ℃ 10 Years
EEEND Endurance TJ = -40 to 150 ℃ 1000 Cycles
TJ = -40 to 85 ℃ 20000 Cycles
PROTECTION CIRCUITS
VUVLO Supply under voltage lockout (UVLO) VM rising 4.3 4.4 4.51 V
VM falling 4.1 4.2 4.3 V
VUVLO_HYS Supply under voltage lockout hysteresis Rising to falling threshold 110 200 350 mV
tUVLO Supply under voltage deglitch time 3 5 7 µs
VOVP Supply over voltage protection (OVP) threshold Supply rising, OVP_EN = 1, OVP_SEL = 0 32.5 34 35 V
Supply falling, OVP_EN = 1, OVP_SEL = 0 31.8 33 34.3 V
Supply rising, OVP_EN = 1, OVP_SEL = 1 20 22 23 V
Supply falling, OVP_EN = 1, OVP_SEL = 1 19 21 22 V
VOVP_HYS Supply over voltage protection hysteresis Rising to falling threshold, OVP_SEL = 1 0.9 1 1.1 V
Rising to falling threshold, OVP_SEL = 0 0.7 0.8 0.9 V
tOVP Supply over voltage deglitch time 2.5 5 7 µs
VCPUV Charge pump under voltage lockout (above VM) Supply rising 2.25 2.5 2.75 V
Supply falling 2.2 2.4 2.6 V
VCPUV_HYS Charge pump UVLO hysteresis Rising to falling threshold 65 100 150 mV
VAVDD_UV Analog regulator (AVDD) under voltage lockout Supply rising 2.7 2.85 3 V
Supply falling 2.5 2.65 2.8 V
VAVDD_UV_HYS Analog regulator under voltage lockout hysteresis Rising to falling threshold 180 200 240 mV
IOCP Over current protection trip point OCP_LVL = 0b 5.5 9 12 A
OCP_LVL = 1b 9 13 18 A
tOCP Over current protection deglitch time OCP_DEG = 00b 0.02 0.2 0.4 µs
OCP_DEG = 01b 0.2 0.6 1.2 µs
OCP_DEG = 10b 0.5 1.2 1.8 µs
OCP_DEG = 11b 0.9 1.6 2.5 µs
tRETRY Over current protection retry time OCP_RETRY = 0 4 5 6 ms
OCP_RETRY = 1 425 500 575 ms
TOTW Thermal warning temperature Die temperature (TJ) 135 145 155 °C
TOTW_HYS Thermal warning hysteresis Die temperature (TJ) 20 25 30 °C
TTSD_BUCK Thermal shutdown temperature (Buck) Die temperature (TJ) 170 180 190 °C
TTSD_BUCK_HYS Thermal shutdown hysteresis (Buck) Die temperature (TJ) 20 25 30 °C
TTSD Thermal shutdown temperature (FET) Die temperature (TJ) 165 175 185 °C
TTSD_HYS Thermal shutdown hysteresis (FET) Die temperature (TJ) 20 25 30 °C
(1) RLBK is resistance of inductor LBK.
(2) If AVDD is switched off, I/O pins must not obstruct the SDA and SCL lines.
(3) The maximum tf for the SDA and SCL bus lines (300 ns) is longer than the specified maximum tof for the output stages (250 ns). This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
(4) Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.