SLLSFS3 Data sheet

SLLSFS3 May 2024 MCT8316A-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGF|40
- MPQF173F

Thermal pad, mechanical data (Package|Pins)

RGF|40
- QFND710

Orderable Information

sllsfs3_oa

6.7.3 Hardware_Configuration Registers

Table 6-29 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset addresses not listed in Table 6-29 should be considered as reserved locations and the register contents should not be modified.

Table 6-29 HARDWARE_CONFIGURATION Registers

Offset	Acronym	Register Name	Section
A4h	PIN_CONFIG1	Hardware pin configuration	Section 6.7.3.1
A6h	PIN_CONFIG2	Hardware pin configuration	Section 6.7.3.2
A8h	DEVICE_CONFIG	Device configuration	Section 6.7.3.3

Complex bit access types are encoded to fit into small table cells. Table 6-30 shows the codes that are used for access types in this section.

Table 6-30 Hardware_Configuration Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.7.3.1 PIN_CONFIG1 Register (Offset = A4h) [Reset = 00000000h]

PIN_CONFIG1 is shown in Figure 6-68 and described in Table 6-31.

Return to the Summary Table.

Figure 6-68 PIN_CONFIG1 Register

31	30	29	28	27	26	25	24
PARITY	DACOUT1_VAR_ADDR
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
DACOUT1_VAR_ADDR					DACOUT2_VAR_ADDR
R/W-0h					R/W-0h

15	14	13	12	11	10	9	8
DACOUT2_VAR_ADDR
R/W-0h

7	6	5	4	3	2	1	0
DACOUT2_VAR_ADDR	BRAKE_INPUT		DIR_INPUT		SPD_CTRL_MODE		RESERVED
R/W-0h	R/W-0h		R/W-0h		R/W-0h		R-0h

Table 6-31 PIN_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-19	DACOUT1_VAR_ADDR	R/W	0h	12-bit address of variable to be monitored
18-7	DACOUT2_VAR_ADDR	R/W	0h	12-bit address of variable to be monitored
6-5	BRAKE_INPUT	R/W	0h	Brake input configuration 0h = Hardware Pin BRAKE 1h = Overwrite Hardware pin with Active Brake 2h = Overwrite Hardware pin with brake functionality disabled 3h = N/A
4-3	DIR_INPUT	R/W	0h	Direction input configuration 0h = Hardware Pin DIR 1h = Overwrite Hardware pin with clockwise rotation OUTA-OUTB-OUTC 3h = N/A
2-1	SPD_CTRL_MODE	R/W	0h	Speed input configuration 0h = Analog mode speed Input 1h = PWM Mode Speed Input 2h = I2C Speed Input mode 3h = Frequency based speed Input mode
0	RESERVED	R	0h	Reserved

6.7.3.2 PIN_CONFIG2 Register (Offset = A6h) [Reset = 00000000h]

PIN_CONFIG2 is shown in Figure 6-69 and described in Table 6-32.

Return to the Summary Table.

Figure 6-69 PIN_CONFIG2 Register

31	30	29	28	27	26	25	24
PARITY	DAC_SOX_CONFIG		RESERVED	DAC_XTAL_CONFIG	RESERVED
R/W-0h	R/W-0h		R-0h	R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED				SLEEP_TIME		EXT_WD_EN	EXT_WD_INPUT
R-0h				R/W-0h		R/W-0h	R/W-0h

15	14	13	12	11	10	9	8
EXT_WD_FAULT	EXT_WD_FREQ		RESERVED
R/W-0h	R/W-0h		R-0h

7	6	5	4	3	2	1	0
RESERVED
R-0h

Table 6-32 PIN_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-29	DAC_SOX_CONFIG	R/W	0h	Pin 36 configuration 0h = DACOUT2 1h = SOA 2h = SOB 3h = SOC
28	RESERVED	R	0h	Reserved
27	DAC_XTAL_CONFIG	R/W	0h	Pin 37 and pin 38 configuration 0h = N/A 1h = Pin 37 as DACOUT1 and pin 38 as DACOUT2
26-20	RESERVED	R	0h	Reserved
19-18	SLEEP_TIME	R/W	0h	Sleep entry time 0h = Check low for 50 µs 1h = Check low for 200 µs 2h = Check low for 20 ms 3h = Check low for 200 ms
17	EXT_WD_EN	R/W	0h	Enable external watchdog 0h = Disable 1h = Enable
16	EXT_WD_INPUT	R/W	0h	External watchdog source 0h = I2C 1h = GPIO
15	EXT_WD_FAULT	R/W	0h	External watchdog fault mode 0h = Report only 1h = Latched fault with Hi-Z outputs
14-13	EXT_WD_FREQ	R/W	0h	External watchdog frequency 0h = 10Hz 1h = 5Hz 2h = 2Hz 3h = 1Hz
12-0	RESERVED	R	0h	Reserved

6.7.3.3 DEVICE_CONFIG Register (Offset = A8h) [Reset = 00000000h]

DEVICE_CONFIG is shown in Figure 6-70 and described in Table 6-33.

Return to the Summary Table.

Figure 6-70 DEVICE_CONFIG Register

31	30	29	28	27	26	25	24
PARITY	INPUT_MAX_FREQUENCY
R/W-0h	R/W-0h

23	22	21	20	19	18	17	16
INPUT_MAX_FREQUENCY
R/W-0h

15	14	13	12	11	10	9	8
STL_ENABLE	SSM_CONFIG	RESERVED		DEV_MODE	SPD_PWM_RANGE_SELECT	CLK_SEL
R/W-0h	R/W-0h	R-0h		R/W-0h	R/W-0h	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	EXT_CLK_EN	EXT_CLK_CONFIG			RESERVED
R-0h	R/W-0h	R/W-0h			R-0h

Table 6-33 DEVICE_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PARITY	R/W	0h	Parity bit
30-16	INPUT_MAX_FREQUENCY	R/W	0h	Maximum frequency (in Hz) for frequency based speed input
15	STL_ENABLE	R/W	0h	STL enable 0h = Disable 1h = Enable
14	SSM_CONFIG	R/W	0h	SSM enable 0h = Enable 1h = Disable
13-12	RESERVED	R	0h	Reserved
11	DEV_MODE	R/W	0h	Device mode select 0h = Standby mode 1h = Sleep mode
10	SPD_PWM_RANGE_SELECT	R/W	0h	PWM frequency range select 0h = 325 Hz to 95 kHz speed PWM input 1h = 10 Hz to 325 Hz speed PWM input
9-8	CLK_SEL	R/W	0h	Clock source 0h = Internal Oscillator 1h = N/A 2h = N/A 3h = External Clock input
7	RESERVED	R	0h	Reserved
6	EXT_CLK_EN	R/W	0h	External clock enable 0h = Disable 1h = Enable
5-3	EXT_CLK_CONFIG	R/W	0h	External clock frequency 0h = 8 kHz 1h = 16 kHz 2h = 32 kHz 3h = 64 kHz 4h = 128 kHz 5h = 256 kHz 6h = 512 kHz 7h = 1024 kHz
2-0	RESERVED	R	0h	Reserved