SLLSFS3 May   2024 MCT8316A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings Auto
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Output Stage
      2. 6.3.2  Device Interface Modes
        1. 6.3.2.1 Interface - Control and Monitoring
        2. 6.3.2.2 I2C Interface
      3. 6.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 6.3.3.1 Buck in Inductor Mode
        2. 6.3.3.2 Buck in Resistor mode
        3. 6.3.3.3 Buck Regulator with External LDO
        4. 6.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 6.3.3.5 Mixed Mode Buck Operation and Control
        6. 6.3.3.6 Buck Undervoltage Protection
        7. 6.3.3.7 Buck Overcurrent Protection
      4. 6.3.4  AVDD Linear Voltage Regulator
      5. 6.3.5  Charge Pump
      6. 6.3.6  Slew Rate Control
      7. 6.3.7  Cross Conduction (Dead Time)
      8. 6.3.8  SPEED Control
        1. 6.3.8.1 Analog-Mode Speed Control
        2. 6.3.8.2 PWM-Mode Speed Control
        3. 6.3.8.3 I2C based Speed Control
        4. 6.3.8.4 Frequency-Mode Speed Control
      9. 6.3.9  Starting the Motor Under Different Initial Conditions
        1. 6.3.9.1 Case 1 – Motor is Stationary
        2. 6.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 6.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 6.3.10 Motor Start Sequence (MSS)
        1. 6.3.10.1 Initial Speed Detect (ISD)
        2. 6.3.10.2 Motor Resynchronization
        3. 6.3.10.3 Reverse Drive
        4. 6.3.10.4 Motor Start-up
          1. 6.3.10.4.1 Align
          2. 6.3.10.4.2 Double Align
          3. 6.3.10.4.3 Initial Position Detection (IPD)
            1. 6.3.10.4.3.1 IPD Operation
            2. 6.3.10.4.3.2 IPD Release Mode
            3. 6.3.10.4.3.3 IPD Advance Angle
          4. 6.3.10.4.4 Slow First Cycle Startup
          5. 6.3.10.4.5 Open loop
          6. 6.3.10.4.6 Transition from Open to Closed Loop
      11. 6.3.11 Closed Loop Operation
        1. 6.3.11.1 120o Commutation
          1. 6.3.11.1.1 High-Side Modulation
          2. 6.3.11.1.2 Low-Side Modulation
          3. 6.3.11.1.3 Mixed Modulation
        2. 6.3.11.2 Variable Commutation
        3. 6.3.11.3 Lead Angle Control
        4. 6.3.11.4 Closed loop accelerate
      12. 6.3.12 Speed Loop
      13. 6.3.13 Input Power Regulation
      14. 6.3.14 Anti-Voltage Surge (AVS)
      15. 6.3.15 Output PWM Switching Frequency
      16. 6.3.16 Fast Start-up (< 50 ms)
        1. 6.3.16.1 BEMF Threshold
        2. 6.3.16.2 Dynamic Degauss
      17. 6.3.17 Fast Deceleration
      18. 6.3.18 Active Demagnetization
        1. 6.3.18.1 Active Demagnetization in action
      19. 6.3.19 Motor Stop Options
        1. 6.3.19.1 Coast (Hi-Z) Mode
        2. 6.3.19.2 Recirculation Mode
        3. 6.3.19.3 Low-Side Braking
        4. 6.3.19.4 High-Side Braking
        5. 6.3.19.5 Active Spin-Down
      20. 6.3.20 FG Configuration
        1. 6.3.20.1 FG Output Frequency
        2. 6.3.20.2 FG Open-Loop and Lock Behavior
      21. 6.3.21 Protections
        1. 6.3.21.1  VM Supply Undervoltage Lockout
        2. 6.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 6.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 6.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 6.3.21.5  Overvoltage Protection (OVP)
        6. 6.3.21.6  Overcurrent Protection (OCP)
          1. 6.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 6.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 6.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 6.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 6.3.21.7  Buck Overcurrent Protection
        8. 6.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 6.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 6.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 6.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 6.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 6.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 6.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 6.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 6.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 6.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 6.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 6.3.21.10 Thermal Warning (OTW)
        11. 6.3.21.11 Thermal Shutdown (TSD)
        12. 6.3.21.12 Motor Lock (MTR_LCK)
          1. 6.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 6.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 6.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 6.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 6.3.21.13 Motor Lock Detection
          1. 6.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 6.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 6.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 6.3.21.14 IPD Faults
    4. 6.4 Device Functional Modes
      1. 6.4.1 Functional Modes
        1. 6.4.1.1 Sleep Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Fault Reset (CLR_FLT)
    5. 6.5 External Interface
      1. 6.5.1 DRVOFF Functionality
      2. 6.5.2 DAC outputs
      3. 6.5.3 SOX Output
      4. 6.5.4 Oscillator Source
        1. 6.5.4.1 External Clock Source
      5. 6.5.5 External Watchdog
    6. 6.6 EEPROM access and I2C interface
      1. 6.6.1 EEPROM Access
        1. 6.6.1.1 EEPROM Write
        2. 6.6.1.2 EEPROM Read
      2. 6.6.2 I2C Serial Interface
        1. 6.6.2.1 I2C Data Word
        2. 6.6.2.2 I2C Write Operation
        3. 6.6.2.3 I2C Read Operation
        4. 6.6.2.4 Examples of MCT8316A-Q1 I2C Communication Protocol Packets
        5. 6.6.2.5 Internal Buffers
        6. 6.6.2.6 CRC Byte Calculation
    7. 6.7 EEPROM (Non-Volatile) Register Map
      1. 6.7.1 Algorithm_Configuration Registers
      2. 6.7.2 Fault_Configuration Registers
      3. 6.7.3 Hardware_Configuration Registers
      4. 6.7.4 Gate_Driver_Configuration Registers
    8. 6.8 RAM (Volatile) Register Map
      1. 6.8.1 Fault_Status Registers
      2. 6.8.2 System_Status Registers
      3. 6.8.3 Algo_Control Registers
      4. 6.8.4 Device_Control Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Application Curves
        1. 7.2.1.1 Motor startup
        2. 7.2.1.2 120o and variable commutation
        3. 7.2.1.3 Faster startup time
        4. 7.2.1.4 Setting the BEMF threshold
        5. 7.2.1.5 Maximum speed
        6. 7.2.1.6 Faster deceleration
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 Power Dissipation
  9. 8 Device and Documentation Support
    1. 8.1 Support Resources
    2. 8.2 Trademarks
    3. 8.3 Electrostatic Discharge Caution
    4. 8.4 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

MCT8316A-Q1 MCT8316A-Q1 40-Pin VQFN With Exposed Thermal Pad Top View Figure 4-1 MCT8316A-Q1 40-Pin VQFN With Exposed Thermal Pad Top View
Table 4-1 Pin Functions
PIN 40-pin Package TYPE(1) DESCRIPTION
NAME MCT8316A-Q1
AGND 26 GND Device analog ground. Refer Layout Guidelines for connections recommendation.
AVDD 27 PWR O 3.3V internal regulator output. Connect a X5R or X7R, 1µF, 6.3V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 20mA externally.
BRAKE 35 I High → brake the motor
Low → normal operation

Connect to PGND via 10kΩ resistor, if not used
CP 8 PWR Charge pump output. Connect a X5R or X7R, 1µF, 16V ceramic capacitor between the CP and VM pins.
CPH 7 PWR Charge pump switching node. Connect a X5R or X7R, 47nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
CPL 6 PWR
DACOUT2/SOX 36 O Multipurpose pin:
DAC output when configured as DACOUT2
CSA output configured as SOX
DACOUT1 37 O DAC output DACOUT1
DACOUT2 38 O DAC output DACOUT2
DGND 2 GND Device digital ground. Refer Layout Guidelines for connections recommendation.
DIR 34 I Direction of motor spinning;
When low, phase driving sequence is OUT A → OUT B → OUT C
When high, phase driving sequence is OUT A → OUT C → OUT B

Connect to PGND via 10kΩ resistor, if not used
DRVOFF 21 I Coast (Hi-Z) all six MOSFETs.
DVDD 1 PWR 1.5V internal regulator output. Connect a X5R or X7R, 1µF, 6.3V ceramic capacitor between the DVDD and DGND pins.
EXT_CLK 33 I External clock reference input in external clock reference mode.
EXT_WD 32 I External watchdog input.
FB_BK 3 PWR I/O Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor.
FG 29 O Motor speed indicator output. Open-drain output requires an external pull-up resistor to 3.3V to 5V.
GND_BK 4 GND Buck regulator ground. Refer Layout Guidelines for connections recommendation.
NC 22, 23, 24, 25, 39 - No connection, open
nFAULT 40 O Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 3.3V to 5V.
OUTA 13, 14 PWR O Half bridge output A
OUTB 16, 17 PWR O Half bridge output B
OUTC 19, 20 PWR O Half bridge output C
PGND 12, 15, 18 GND Device power ground. Refer Layout Guidelines for connections recommendation.
SCL 31 I I2C clock input
SDA 30 I/O I2C data line
SPEED/WAKE 28 I Device speed input; supports analog, frequency or PWM speed input. The speed pin input can be configured through SPD_CTRL_MODE.
SW_BK 5 PWR Buck switch node. Connect this pin to an inductor or resistor.
VM 9, 10, 11 PWR I Device and motor power supply. Connect to motor supply voltage; bypass to GND with a 0.1µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
Thermal pad GND Must be connected to AGND
(1) I = input, O = output, GND = ground, PWR = power, NC = no connect