SLLSFS3 May 2024 MCT8316A-Q1
PRODUCTION DATA
If at any time input supply voltage on the VM pins rises higher lower than the VOVP threshold voltage, all the integrated FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT and OVP bits are set to 1b in the status registers. Normal operation resumes (driver operation and the nFAULT pin is released) when the OVP condition clears. The OVP bit stays set until cleared through the CLR_FLT bit. Setting the OVP_EN to 1b enables this protection feature.
The OVP threshold can be set to 20-V or 32-V based on the OVP_SEL bit.