SLLSFQ3 January   2023 MCT8329A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Signal Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 120o Commutation
          1. 7.3.10.1.1 High-Side Modulation
          2. 7.3.10.1.2 Low-Side Modulation
          3. 7.3.10.1.3 Mixed Modulation
        2. 7.3.10.2 Variable Commutation
        3. 7.3.10.3 Lead Angle Control
        4. 7.3.10.4 Closed loop accelerate
      11. 7.3.11 Speed Loop
      12. 7.3.12 Power Loop
      13. 7.3.13 Anti-Voltage Surge (AVS)
      14. 7.3.14 Output PWM Switching Frequency
      15. 7.3.15 Fast Start-up (< 50 ms)
        1. 7.3.15.1 BEMF Threshold
        2. 7.3.15.2 Dynamic Degauss
      16. 7.3.16 Fast Deceleration
      17. 7.3.17 Dynamic Voltage Scaling
      18. 7.3.18 Motor Stop Options
        1. 7.3.18.1 Coast (Hi-Z) Mode
        2. 7.3.18.2 Recirculation Mode
        3. 7.3.18.3 Low-Side Braking
        4. 7.3.18.4 High-Side Braking
        5. 7.3.18.5 Active Spin-Down
      19. 7.3.19 FG Configuration
        1. 7.3.19.1 FG Output Frequency
        2. 7.3.19.2 FG in Open-Loop
        3. 7.3.19.3 FG During Motor Stop
        4. 7.3.19.4 FG Behaviour During Fault
      20. 7.3.20 Protections
        1. 7.3.20.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.20.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.20.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.20.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.20.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.20.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.20.7  Thermal Shutdown (OTSD)
        8. 7.3.20.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.20.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.20.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.20.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.20.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.20.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.20.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.20.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.20.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.20.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.20.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.20.10 Motor Lock (MTR_LCK)
          1. 7.3.20.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.20.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.20.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.20.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.20.11 Motor Lock Detection
          1. 7.3.20.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.20.11.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.20.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.20.12 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2. 8.2.2.2 120o and variable commutation
        3. 8.2.2.3 Faster startup time
        4. 8.2.2.4 Setting the BEMF threshold
        5. 8.2.2.5 Maximum speed
        6. 8.2.2.6 Faster deceleration
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.2 Fault_Configuration Registers

#GUID-20220906-SS0T-1XF2-DDCH-N875VDTJWLW2/FAULT_CONFIGURATION_FAULT_CONFIGURATION_TABLE_1_TABLE lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in #GUID-20220906-SS0T-1XF2-DDCH-N875VDTJWLW2/FAULT_CONFIGURATION_FAULT_CONFIGURATION_TABLE_1_TABLE should be considered as reserved locations and the register contents should not be modified.

Table 7-29 FAULT_CONFIGURATION Registers
OffsetAcronymRegister NameSection
92hFAULT_CONFIG1Fault configuration 1FAULT_CONFIG1 Register (Offset = 92h) [Reset = 00000000h]
94hFAULT_CONFIG2Fault configuration 2FAULT_CONFIG2 Register (Offset = 94h) [Reset = 00000000h]

Complex bit access types are encoded to fit into small table cells. #GUID-20220906-SS0T-1XF2-DDCH-N875VDTJWLW2/FAULT_CONFIGURATION_FAULT_CONFIGURATION_LEGEND_TABLE shows the codes that are used for access types in this section.

Table 7-30 Fault_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.7.2.1 FAULT_CONFIG1 Register (Offset = 92h) [Reset = 00000000h]

FAULT_CONFIG1 is shown in #GUID-20220906-SS0T-1XF2-DDCH-N875VDTJWLW2/FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1_TABLE_TABLE.

Return to the Summary Table.

Register to configure fault settings1

Table 7-31 FAULT_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30-28NO_MTR_DEG_TIMER/W0h No motor detect deglitch time
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
27-24CBC_ILIMIT_MODER/W0h Cycle by cycle current limit. This mode is applied for CBC_ILIMIT, OL_ILIMT, ALIGN_ILIMIT
0h = Automatic recovery next PWM cycle; nFAULT active; driver is in recirculation mode
1h = Automatic recovery next PWM cycle; nFAULT inactive; driver is in recirculation mode
2h = Automatic recovery if current < ILIMIT; nFAULT active; driver is in recriculation mode (Only available with high-side modulation)
3h = Automatic recovery if current < ILIMIT; nFAULT inactive; driver is in recirculation mode (Only available with high-side modulation)
4h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT active; driver is in recirculation mode
5h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT inactive; driver is in recirculation mode
6h = Current > ILIMIT is report only but no action is taken
7h = Cycle by Cycle limit is disabled
8h = Cycle by Cycle limit is disabled
9h = Cycle by Cycle limit is disabled
Ah = Cycle by Cycle limit is disabled
Bh = Cycle by Cycle limit is disabled
Ch = Cycle by Cycle limit is disabled
Dh = Cycle by Cycle limit is disabled
Eh = Cycle by Cycle limit is disabled
Fh = Cycle by Cycle limit is disabled
23-19LOCK_ILIMITR/W0h Lock current threshold (Lock current threshold (A) = Lock_CURR_THR / CSA_GAIN*RSHUNT)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
11h = 1.7 V
12h = 1.8 V
13h = 1.9 V
14h = 2.0 V
15h = 2.1 V
16h = 2.2 V
17h = 2.3 V
18h = 2.4 V
19h = 2.5 V
1Ah = 2.6 V
1Bh = 2.7 V
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
18-15LOCK_ILIMIT_MODER/W0h Lock detection current limit mode
0h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated
1h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in recirculation mode
2h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high-side brake mode (All high-side FETs are turned ON)
3h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low-side brake mode (All low-side FETs are turned ON)
4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated
5h = Automatic recovery after tLCK_RETRY; Gate driver is in recirculation mode
6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-side brake mode (All high-side FETs are turned ON)
7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-side brake mode (All low-side FETs are turned ON)
8h = Ilimit lock detection is in report only but no action is taken
9h = Ilimit lock detection is disabled
Ah = Ilimit lock detection is disabled
Bh = Ilimit lock detection is disabled
Ch = Ilimit lock detection is disabled
Dh = Ilimit lock detection is disabled
Eh = Ilimit lock detection is disabled
Fh = Ilimit lock detection is disabled
14-11LOCK_ILIMIT_DEGR/W0h Lock detection current limit deglitch time
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 25 ms
5h = 50 ms
6h = 75 ms
7h = 100 ms
8h = 250 ms
9h = 500 ms
Ah = 1 s
Bh = 2.5 s
Ch = 5 s
Dh = 10 s
Eh = 25 s
Fh = 50 s
10-8CBC_RETRY_PWM_CYCR/W0h Number of PWM cycles for CBC current limit to retry
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
7RESERVEDR/W0h Reserved
6-3MTR_LCK_MODER/W0h Motor lock mode
0h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated
1h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in recirculation mode
2h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in high-side brake mode (All high-side FETs are turned ON)
3h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low-side brake mode (All low-side FETs are turned ON)
4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated
5h = Automatic recovery after tLCK_RETRY; Gate driver is in recirculation mode
6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-side brake mode (All high-side FETs are turned ON)
7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-side brake mode (All low-side FETs are turned ON)
8h = Motor lock detection is in report only but no action is taken
9h = Motor lock detection is disabled
Bh = Motor lock detection is disabled
Ch = Motor lock detection is disabled
Dh = Motor lock detection is disabled
Eh = Motor lock detection is disabled
Fh = Motor lock detection is disabled
2-0LCK_RETRYR/W0h Lock retry time
0h = 100 ms
1h = 500 ms
2h = 1000 ms
3h = 2000 ms
4h = 3000 ms
5h = 5000 ms
6h = 7500 ms
7h = 10000 ms

7.7.2.2 FAULT_CONFIG2 Register (Offset = 94h) [Reset = 00000000h]

FAULT_CONFIG2 is shown in #GUID-20220906-SS0T-1XF2-DDCH-N875VDTJWLW2/FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2_TABLE_TABLE.

Return to the Summary Table.

Register to configure fault settings2

Table 7-32 FAULT_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30ABN_SPD_ENR/W0h Abnormal SpeedEnable
0h = Disable
1h = Enable
29LOSS_OF_SYNC_ENR/W0h Loss of Sync Enable
0h = Disable
1h = Enable
28NO_MOTOR_ENR/W0h No Motor Enable
0h = Disable
1h = Enable
27-24LOCK_ABN_SPEEDR/W0h Abnornal speed lock threshold
0h = 250 Hz
1h = 500 Hz
2h = 750 Hz
3h = 1000 Hz
4h = 1250 Hz
5h = 1500 Hz
6h = 1750 Hz
7h = 2000 Hz
8h = 2250 Hz
9h = 2500 Hz
Ah = 2750 Hz
Bh = 3000 Hz
Ch = 3250 Hz
Dh = 3500 Hz
Eh = 3750 Hz
Fh = 4000 Hz
23-21LOSS_SYNC_TIMESR/W0h Number of times sync lost for loss of sync lock fault
0h = Trigger after losing sync 2 times
1h = Trigger after losing sync 3 times
2h = Trigger after losing sync 4 times
3h = Trigger after losing sync 5 times
4h = Trigger after losing sync 6 times
5h = Trigger after losing sync 7 times
6h = Trigger after losing sync 8 times
7h = Trigger after losing sync 9 times
20-18NO_MTR_THRR/W0h Lock current threshold. Lock current threshold (A) = Lock_CURR_THR / (CSA_GAIN * RSENSE)
0h = 0.005 V
1h = 0.0075 V
2h = 0.010 V
3h = 0.0125 V
4h = 0.020 V
5h = 0.025 V
6h = 0.030 V
7h = 0.04 V
17MAX_VM_MODER/W0h
0h = Latch on Overvoltage
1h = Automatic clear if voltage in bounds
16-14MAX_VM_MOTORR/W0h Maximum voltage for running motor
0h = No Limit
1h = 10.0 V
2h = 15.0 V
3h = 22.0 V
4h = 32.0 V
5h = 40.0 V
6h = 50.0 V
7h = 60.0 V
13MIN_VM_MODER/W0h
0h = Latch on Undervoltage
1h = Automatic clear if voltage in bounds
12-10MIN_VM_MOTORR/W0h Minimum voltage for running motor
0h = No Limit
1h = 5.0 V
2h = 6.0 V
3h = 7.0 V
4h = 8.0 V
5h = 10.0 V
6h = 12.0 V
7h = 15.0 V
9-7AUTO_RETRY_TIMESR/W0h Number of automatic retry attempts for LOCK Faults
0h = No Limit
1h = 2
2h = 3
3h = 5
4h = 7
5h = 10
6h = 15
7h = 20
6-4LOCK_MIN_SPEEDR/W0h Speed below which lock fault is triggered
0h = 0.5 Hz
1h = 1 Hz
2h = 2 Hz
3h = 3 Hz
4h = 5 Hz
5h = 10 Hz
6h = 15 Hz
7h = 25 Hz
3-2ABN_LOCK_SPD_RATIOR/W0h Ratio of electrical speed between two consecutive cycles above which abnormal speed lock fault is triggered
0h = 2
1h = 4
2h = 6
3h = 8
1-0ZERO_DUTY_THRR/W0h Duty cycle below which target speed is zero
0h = 0%
1h = 1%
2h = 2.0%
3h = 2.5%