SLLSFQ3 January 2023 MCT8329A
PRODUCTION DATA
#GUID-20220906-SS0T-N6QC-GXT2-9QNRCPPQVSZC/DEVICE_CONTROL_DEVICE_CONTROL_TABLE_1_TABLE lists the memory-mapped registers for the Device_Control registers. All register offset addresses not listed in #GUID-20220906-SS0T-N6QC-GXT2-9QNRCPPQVSZC/DEVICE_CONTROL_DEVICE_CONTROL_TABLE_1_TABLE should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
E8h | DEVICE_CTRL | Device Control Parameters | DEVICE_CTRL Register (Offset = E8h) [Reset = 00000000h] |
Complex bit access types are encoded to fit into small table cells. #GUID-20220906-SS0T-N6QC-GXT2-9QNRCPPQVSZC/DEVICE_CONTROL_DEVICE_CONTROL_LEGEND_TABLE shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DEVICE_CTRL is shown in #GUID-20220906-SS0T-N6QC-GXT2-9QNRCPPQVSZC/DEVICE_CONTROL_DEVICE_CONTROL_DEVICE_CONTROL_DEVICE_CTRL_TABLE_TABLE.
Return to the Summary Table.
Device Control Parameters
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | W | 0h | Reserved |
30-16 | SPEED_CTRL | W | 0h | Digital speed command. (SPEED_CTRL (%) = SPEED_CTRL/32767 * 100%) |
15 | OVERRIDE | W | 0h | Speed input select for I2C vs speed pin
0h = SPEED_CMD using Analog/Freq/PWM mode 1h = SPEED_CMD using SPD_CTRL[14:0] |
14-0 | RESERVED | R | 0h | Reserved |