SLLSFQ3 January   2023 MCT8329A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Comm
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 1pkg
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Three Phase BLDC Gate Drivers
      2. 7.3.2  Gate Drive Architecture
        1. 7.3.2.1 Dead time and Cross Conduction Prevention
      3. 7.3.3  AVDD Linear Voltage Regulator
      4. 7.3.4  DVDD Voltage Regulator
        1. 7.3.4.1 AVDD Powered VREG
        2. 7.3.4.2 External Supply for VREG
        3. 7.3.4.3 External MOSFET for VREG Supply
      5. 7.3.5  Low-Side Current Sense Amplifier
      6. 7.3.6  Device Interface Modes
        1. 7.3.6.1 Interface - Control and Monitoring
        2. 7.3.6.2 I2C Interface
      7. 7.3.7  Motor Control Input Options
        1. 7.3.7.1 Analog-Mode Motor Control
        2. 7.3.7.2 PWM-Mode Motor Control
        3. 7.3.7.3 Frequency-Mode Motor Control
        4. 7.3.7.4 I2C based Motor Control
        5. 7.3.7.5 Input Control Signal Profiles
          1. 7.3.7.5.1 Linear Control Profiles
          2. 7.3.7.5.2 Staircase Control Profiles
          3. 7.3.7.5.3 Forward-Reverse Profiles
        6. 7.3.7.6 Control Input Transfer Function without Profiler
      8. 7.3.8  Starting the Motor Under Different Initial Conditions
        1. 7.3.8.1 Case 1 – Motor is Stationary
        2. 7.3.8.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.8.3 Case 3 – Motor is Spinning in the Reverse Direction
      9. 7.3.9  Motor Start Sequence (MSS)
        1. 7.3.9.1 Initial Speed Detect (ISD)
        2. 7.3.9.2 Motor Resynchronization
        3. 7.3.9.3 Reverse Drive
        4. 7.3.9.4 Motor Start-up
          1. 7.3.9.4.1 Align
          2. 7.3.9.4.2 Double Align
          3. 7.3.9.4.3 Initial Position Detection (IPD)
            1. 7.3.9.4.3.1 IPD Operation
            2. 7.3.9.4.3.2 IPD Release
            3. 7.3.9.4.3.3 IPD Advance Angle
          4. 7.3.9.4.4 Slow First Cycle Startup
          5. 7.3.9.4.5 Open loop
          6. 7.3.9.4.6 Transition from Open to Closed Loop
      10. 7.3.10 Closed Loop Operation
        1. 7.3.10.1 120o Commutation
          1. 7.3.10.1.1 High-Side Modulation
          2. 7.3.10.1.2 Low-Side Modulation
          3. 7.3.10.1.3 Mixed Modulation
        2. 7.3.10.2 Variable Commutation
        3. 7.3.10.3 Lead Angle Control
        4. 7.3.10.4 Closed loop accelerate
      11. 7.3.11 Speed Loop
      12. 7.3.12 Power Loop
      13. 7.3.13 Anti-Voltage Surge (AVS)
      14. 7.3.14 Output PWM Switching Frequency
      15. 7.3.15 Fast Start-up (< 50 ms)
        1. 7.3.15.1 BEMF Threshold
        2. 7.3.15.2 Dynamic Degauss
      16. 7.3.16 Fast Deceleration
      17. 7.3.17 Dynamic Voltage Scaling
      18. 7.3.18 Motor Stop Options
        1. 7.3.18.1 Coast (Hi-Z) Mode
        2. 7.3.18.2 Recirculation Mode
        3. 7.3.18.3 Low-Side Braking
        4. 7.3.18.4 High-Side Braking
        5. 7.3.18.5 Active Spin-Down
      19. 7.3.19 FG Configuration
        1. 7.3.19.1 FG Output Frequency
        2. 7.3.19.2 FG in Open-Loop
        3. 7.3.19.3 FG During Motor Stop
        4. 7.3.19.4 FG Behaviour During Fault
      20. 7.3.20 Protections
        1. 7.3.20.1  PVDD Supply Undervoltage Lockout (PVDD_UV)
        2. 7.3.20.2  AVDD Power on Reset (AVDD_POR)
        3. 7.3.20.3  GVDD Undervoltage Lockout (GVDD_UV)
        4. 7.3.20.4  BST Undervoltage Lockout (BST_UV)
        5. 7.3.20.5  MOSFET VDS Overcurrent Protection (VDS_OCP)
        6. 7.3.20.6  VSENSE Overcurrent Protection (SEN_OCP)
        7. 7.3.20.7  Thermal Shutdown (OTSD)
        8. 7.3.20.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.20.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.20.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.20.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.20.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.20.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.20.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.20.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.20.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.20.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.20.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.20.10 Motor Lock (MTR_LCK)
          1. 7.3.20.10.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.20.10.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.20.10.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.20.10.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        11. 7.3.20.11 Motor Lock Detection
          1. 7.3.20.11.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.20.11.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.20.11.3 Lock3: No-Motor Fault (NO_MTR)
        12. 7.3.20.12 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF - Gate Driver Shutdown Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Amplifier Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1.      Detailed Design Procedure
      2.      Bootstrap Capacitor and GVDD Capacitor Selection
      3. 8.2.1 Selection of External MOSFET for VREG Power Supply
      4.      Gate Drive Current
      5.      Gate Resistor Selection
      6.      System Considerations in High Power Designs
      7.      Capacitor Voltage Ratings
      8.      External Power Stage Components
      9. 8.2.2 Application curves
        1. 8.2.2.1 Motor startup
        2. 8.2.2.2 120o and variable commutation
        3. 8.2.2.3 Faster startup time
        4. 8.2.2.4 Setting the BEMF threshold
        5. 8.2.2.5 Maximum speed
        6. 8.2.2.6 Faster deceleration
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.1 Algorithm_Configuration Registers

#GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TABLE_1_TABLE lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses not listed in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_TABLE_1_TABLE should be considered as reserved locations and the register contents should not be modified.

Table 7-10 ALGORITHM_CONFIGURATION Registers
Offset Acronym Register Name Section
80h ISD_CONFIG ISD configuration ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]
82h MOTOR_STARTUP1 Motor start-up configuration 1 MOTOR_STARTUP1 Register (Offset = 82h) [Reset = 00000000h]
84h MOTOR_STARTUP2 Motor start-up configuration 2 MOTOR_STARTUP2 Register (Offset = 84h) [Reset = 00000000h]
86h CLOSED_LOOP1 Closed loop configuration 1 CLOSED_LOOP1 Register (Offset = 86h) [Reset = 00000000h]
88h CLOSED_LOOP2 Closed loop configuration 2 CLOSED_LOOP2 Register (Offset = 88h) [Reset = 00000000h]
8Ah CLOSED_LOOP3 Closed loop configuration 3 CLOSED_LOOP3 Register (Offset = 8Ah) [Reset = 000000A0h]
8Ch CLOSED_LOOP4 Closed loop configuration 4 CLOSED_LOOP4 Register (Offset = 8Ch) [Reset = 00000000h]
8Eh CONST_SPEED Constant speed configuration CONST_SPEED Register (Offset = 8Eh) [Reset = 00000000h]
90h CONST_PWR Constant power configuration CONST_PWR Register (Offset = 90h) [Reset = 00000000h]
96h 150_DEG_TWO_PH_PROFILE 150° Two-ph profile 150_DEG_TWO_PH_PROFILE Register (Offset = 96h) [Reset = 00000000h]
98h 150_DEG_THREE_PH_PROFILE 150° Three-ph profile 150_DEG_THREE_PH_PROFILE Register (Offset = 98h) [Reset = 00000000h]
9Ah REF_PROFILES1 Speed Profile Configuration1 REF_PROFILES1 Register (Offset = 9Ah) [Reset = X]
9Ch REF_PROFILES2 Speed Profile Configuration2 REF_PROFILES2 Register (Offset = 9Ch) [Reset = X]
9Eh REF_PROFILES3 Speed Profile Configuration3 REF_PROFILES3 Register (Offset = 9Eh) [Reset = X]
A0h REF_PROFILES4 Speed Profile Configuration4 REF_PROFILES4 Register (Offset = A0h) [Reset = X]
A2h REF_PROFILES5 Speed Profile Configuration5 REF_PROFILES5 Register (Offset = A2h) [Reset = X]
A4h REF_PROFILES6 Speed Profile Configuration6 REF_PROFILES6 Register (Offset = A4h) [Reset = X]

Complex bit access types are encoded to fit into small table cells. #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_LEGEND_TABLE shows the codes that are used for access types in this section.

Table 7-11 Algorithm_Configuration Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

7.7.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]

ISD_CONFIG is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ISD_CONFIG_TABLE_TABLE.

Return to the Summary Table.

Register to configure initial speed detect settings

Table 7-12 ISD_CONFIG Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30 ISD_EN R/W 0h ISD enable
0h = Disable
1h = Enable
29 BRAKE_EN R/W 0h Brake enable
0h = Disable
1h = Enable
28 HIZ_EN R/W 0h Hi-Z enable
0h = Disable
1h = Enable
27 RVS_DR_EN R/W 0h Reverse Resynchronization enable
0h = Disable
1h = Enable
26 RESYNC_EN R/W 0h Forward Resynchronization enable
0h = Disable
1h = Enable
25 STAT_BRK_EN R/W 0h Enable or disable brake during stationary
0h = Disable
1h = Enable
24-22 STAT_DETECT_THR R/W 0h Stationary BEMF detect threshold, phase voltage scaled down based on DYN_VOLT_SCALING_EN
0h = 5 mV
1h = 10 mV
2h = 15 mV
3h = 20 mV
4h = 25 mV
5h = 30 mV
6h = 50 mV
7h = 100 mV
21 BRK_MODE R/W 0h Brake mode
0h = All three low-side FETs turned ON
1h = All three high-side FETs turned ON
20-17 RESERVED R/W 0h Reserved
16-13 BRK_TIME R/W 0h Brake time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
12-9 HIZ_TIME R/W 0h Hi-Z time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
8-6 STARTUP_BRK_TIME R/W 0h Brake time when motor is stationary
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
5-3 RESYNC_MIN_THRESHOLD R/W 0h Minimum phase BEMF below which the motor is coasted instead of resync
0h = MIN_DUTY * DC_BUS_VOLTAGE
1h = 300 mV
2h = 400 mV
3h = 500 mV
4h = 600 mV
5h = 800 mV
6h = 1000 mV
7h = 1250 mV
2-1 MTR_STARTUP R/W 0h Motor start-up method
0h = Align
1h = Double Align
2h = IPD
3h = Slow first cycle
0 RESERVED R/W 0h Reserved

7.7.1.2 MOTOR_STARTUP1 Register (Offset = 82h) [Reset = 00000000h]

MOTOR_STARTUP1 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP1_TABLE_TABLE.

Return to the Summary Table.

Register to configure motor startup settings1

Table 7-13 MOTOR_STARTUP1 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-27 ALIGN_RAMP_RATE R/W 0h Align voltage ramp rate
0h = 0.1 V/s
1h = 0.2 V/s
2h = 0.5 V/s
3h = 1 V/s
4h = 2.5 V/s
5h = 5 V/s
6h = 7.5 V/s
7h = 10 V/s
8h = 25 V/s
9h = 50 V/s
Ah = 75 V/s
Bh = 100 V/s
Ch = 250 V/s
Dh = 500 V/s
Eh = 750 V/s
Fh = 1000 V/s
26-23 ALIGN_TIME R/W 0h Align time
0h = 5 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 75 ms
5h = 100 ms
6h = 200 ms
7h = 400 ms
8h = 600 ms
9h = 800 ms
Ah = 1 s
Bh = 2 s
Ch = 4 s
Dh = 6 s
Eh = 8 s
Fh = 10 s
22-18 ALIGN_CURR_THR R/W 0h Align current threshold. Align current threshold (A) = (ALIGN_CURR_THR - Offset) / (CSA_GAIN * RSENSE). Offset = 0.075V for VREF_SEL = UNI DIRECTIONAL CSA (Values rolls over after 1Bh). Offset = 0V for VREF_SEL = BI-DIRECTIONAL CSA (Values rolls over after 0Fh)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = 1.6 V
11h = 1.7 V
12h = 1.8 V
13h = 1.9 V
14h = 2.0 V
15h = 2.1 V
16h = 2.2 V
17h = 2.3 V
18h = 2.4 V
19h = 2.5 V
1Ah = 2.6 V
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
17-16 ALIGN_DUTY R/W 0h Duty cycle limit during align
0h = 10 %
1h = 25 %
2h = 50 %
3h = 100 %
15-13 IPD_CLK_FREQ R/W 0h IPD clock frequency
0h = 50 Hz
1h = 100 Hz
2h = 250 Hz
3h = 500 Hz
4h = 1000 Hz
5h = 2000 Hz
6h = 5000 Hz
7h = 10000 Hz
12-8 IPD_CURR_THR R/W 0h IPD current threshold. IPD current threshold (A) = (IPD_CURR_THR - Offset) / (CSA_GAIN * RSENSE). Offset = 0.075V for VREF_SEL = UNI DIRECTIONAL CSA (Values rolls over after 1Bh). Offset = 0V for VREF_SEL = BI-DIRECTIONAL CSA (Values rolls over after 0Fh)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = 1.6 V
11h = 1.7 V
12h = 1.8 V
13h = 1.9 V
14h = 2.0 V
15h = 2.1 V
16h = 2.2 V
17h = 2.3 V
18h = 2.4 V
19h = 2.5 V
1Ah = 2.6 V
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
7-6 IPD_ADV_ANGLE R/W 0h IPD advance angle
0h = 0°
1h = 30°
2h = 60°
3h = 90°
5-4 IPD_REPEAT R/W 0h Number of times IPD is executed
0h = one
1h = average of 2 times
2h = average of 3 times
3h = average of 4 times
3-0 SLOW_FIRST_CYC_FREQ R/W 0h Frequency of first cycle
0h = 0.05 Hz
1h = 0.1 Hz
2h = 0.25 Hz
3h = 0.5 Hz
4h = 1 Hz
5h = 2 Hz
6h = 3 Hz
7h = 5 Hz
8h = 10 Hz
9h = 15 Hz
Bh = 25 Hz
Ch = 50 Hz
Dh = 100 Hz
Eh = 150 Hz
Fh = 200 Hz

7.7.1.3 MOTOR_STARTUP2 Register (Offset = 84h) [Reset = 00000000h]

MOTOR_STARTUP2 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_MOTOR_STARTUP2_TABLE_TABLE.

Return to the Summary Table.

Register to configure motor startup settings2

Table 7-14 MOTOR_STARTUP2 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-28 OL_DUTY R/W 0h Duty cycle limit during open loop
0h = 10%
1h = 15%
2h = 20%
3h = 25%
4h = 30%
5h = 40%
6h = 50%
7h = 100%
27-23 OL_ILIMIT R/W 0h Open Loop current threshold. OL current threshold (A) = (OL_CURR_THR - Offset) / (CSA_GAIN * RSENSE). Offset = 0.075V for VREF_SEL = UNI DIRECTIONAL CSA (Values rolls over after 1Bh). Offset = 0V for VREF_SEL = BI-DIRECTIONAL CSA (Values rolls over after 0Fh)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = 1.6 V
11h = 1.7 V
12h = 1.8 V
13h = 1.9 V
14h = 2.0 V
15h = 2.1 V
16h = 2.2 V
17h = 2.3 V
18h = 2.4 V
19h = 2.5 V
1Ah = 2.6 V
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
22-18 OL_ACC_A1 R/W 0h Open loop acceleration A1
0h = 0.005 Hz/s
1h = 0.01 Hz/s
2h = 0.025 Hz/s
3h = 0.05 Hz/s
4h = 0.1 Hz/s
5h = 0.25 Hz/s
6h = 0.5 Hz/s
7h = 1 Hz/s
8h = 2.5 Hz/s
9h = 5 Hz/s
Ah = 7.5 Hz/s
Bh = 10 Hz/s
Ch = 12.5 Hz/s
Dh = 15 Hz/s
Eh = 20 Hz/s
Fh = 30 Hz/s
10h = 40 Hz/s
11h = 50 Hz/s
12h = 60 Hz/s
13h = 75 Hz/s
14h = 100 Hz/s
15h = 125 Hz/s
16h = 150 Hz/s
17h = 175 Hz/s
18h = 200 Hz/s
19h = 250 Hz/s
1Ah = 300 Hz/s
1Bh = 400 Hz/s
1Ch = 500 Hz/s
1Dh = 750 Hz/s
1Eh = 1000 Hz/s
1Fh = No Limit (32767) Hz/s
17-13 OL_ACC_A2 R/W 0h Open loop acceleration A2
0h = 0.005 Hz/s2
1h = 0.01 Hz/s2
2h = 0.025 Hz/s2
3h = 0.05 Hz/s2
4h = 0.1 Hz/s2
5h = 0.25 Hz/s2
6h = 0.5 Hz/s2
7h = 1 Hz/s2
8h = 2.5 Hz/s2
9h = 5 Hz/s2
Ah = 7.5 Hz/s2
Bh = 10 Hz/s2
Ch = 12.5 Hz/s2
Dh = 15 Hz/s2
Eh = 20 Hz/s2
Fh = 30 Hz/s2
10h = 40 Hz/s2
11h = 50 Hz/s2
12h = 60 Hz/s2
13h = 75 Hz/s2
14h = 100 Hz/s2
15h = 125 Hz/s2
16h = 150 Hz/s2
17h = 175 Hz/s2
18h = 200 Hz/s2
19h = 250 Hz/s2
1Ah = 300 Hz/s2
1Bh = 400 Hz/s2
1Ch = 500 Hz/s2
1Dh = 750 Hz/s2
1Eh = 1000 Hz/s2
1Fh = No Limit (32767) Hz/s2
12-8 OPN_CL_HANDOFF_THR R/W 0h Open to closed loop handoff threshold
0h = 1 Hz
1h = 4 Hz
2h = 8 Hz
3h = 12 Hz
4h = 16 Hz
5h = 20 Hz
6h = 24 Hz
7h = 28 Hz
8h = 32 Hz
9h = 36 Hz
Ah = 40 Hz
Bh = 45 Hz
Ch = 50 Hz
Dh = 55 Hz
Eh = 60 Hz
Fh = 65 Hz
10h = 70 Hz
11h = 75 Hz
12h = 80 Hz
13h = 85 Hz
14h = 90 Hz
15h = 100 Hz
16h = 150 Hz
17h = 200 Hz
18h = 250 Hz
19h = 300 Hz
1Ah = 350 Hz
1Bh = 400 Hz
1Ch = 450 Hz
1Dh = 500 Hz
1Eh = 550 Hz
1Fh = 600 Hz
7 AUTO_HANDOFF R/W 0h Auto handoff enable
0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)
1h = Enable Auto Handoff
6 FIRST_CYCLE_FREQ_SEL R/W 0h First cycle frequency during the Open Loop
0h = Defined by SLOW_FIRST_CYC_FREQ
1h = 0 Hz
5-2 MIN_DUTY R/W 0h Min operational duty cycle
0h = 0%
1h = 1.5 %
2h = 2.5 %
3h = 3 %
4h = 4 %
5h = 5 %
6h = 6 %
7h = 7 %
8h = 8 %
9h = 9 %
Ah = 10 %
Bh = 12 %
Ch = 15 %
Dh = 17.5 %
Eh = 20 %
Fh = 25 %
1-0 OL_HANDOFF_CYCLES R/W 0h Open loop handoff cycles
0h = 3
1h = 6
2h = 12
3h = 24

7.7.1.4 CLOSED_LOOP1 Register (Offset = 86h) [Reset = 00000000h]

CLOSED_LOOP1 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP1_TABLE_TABLE.

Return to the Summary Table.

Register to configure close loop settings1

Table 7-15 CLOSED_LOOP1 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-29 COMM_CONTROL R/W 0h Trapezodial commutation mode
0h = 120° Commutation
1h = Variable commutation between 120° and 150°
2h = N/A
3h = N/A
28-24 CL_ACC R/W 0h Closed loop acceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
23 CL_DEC_CONFIG R/W 0h Closed loop decel configuration
0h = Close loop deceleration defined by CL_DEC
1h = Close loop deceleration defined by CL_ACC
22-18 CL_DEC R/W 0h Closed loop deceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
17-13 PWM_FREQ_OUT R/W 0h Output PWM switching frequency
0h = 5 kHz
1h = 6 kHz
2h = 7 kHz
3h = 8 kHz
4h = 9 kHz
5h = 10 kHz
6h = 11 kHz
7h = 12 kHz
8h = 13 kHz
9h = 14 kHz
Ah = 15 kHz
Bh = 16 kHz
Ch = 17 kHz
Dh = 18 kHz
Eh = 19 kHz
Fh = 20 kHz
10h = 25 kHz
11h = 30 kHz
12h = 35 kHz
13h = 40 kHz
14h = 45 kHz
15h = 50 kHz
16h = 55 kHz
17h = 60 kHz
18h = 65 kHz
19h = 70 kHz
1Ah = 75 kHz
1Bh = 80 kHz
1Ch = 85 kHz
1Dh = 90 kHz
1Eh = 95 kHz
1Fh = 100 kHz
12-11 PWM_MODUL R/W 0h PWM modulation.
0h = High-Side Modulation
1h = Low-Side Modulation
2h = Mixed Modulation
3h = N/A
10 PWM_MODE R/W 0h PWM mode
0h = Single Ended Mode
1h = Complementary Mode
9 LD_ANGLE_POLARITY R/W 0h Polarity of applied lead angle
0h = Lag
1h = Lead
8-1 LD_ANGLE R/W 0h Lead Angle {Lead Angle (deg) = LD_ANGLE * 0.12}
0 RESERVED R/W 0h Reserved

7.7.1.5 CLOSED_LOOP2 Register (Offset = 88h) [Reset = 00000000h]

CLOSED_LOOP2 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP2_TABLE_TABLE.

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Register to configure close loop settings2

Table 7-16 CLOSED_LOOP2 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-29 FG_SEL R/W 0h FG mode select
0h = Output FG in open loop and closed loop
1h = Output FG in only closed loop
2h = Output FG in open loop for the first try.
3h = N/A
28-25 FG_DIV_FACTOR R/W 0h FG division factor
0h = Divide by 3 (2-pole motor mechanical speed*3)
1h = Divide by 1 (2-pole motor mechanical speed)
2h = Divide by 2 (4-pole motor mechanical speed)
3h = Divide by 3 (6-pole motor mechanical speed)
4h = Divide by 4 (8-pole motor mechanical speed)
5h = Divide by 5 (10-pole motor mechanical speed)
6h = Divide by 6 (12-pole motor mechanical speed)
7h = Divide by 7 (14-pole motor mechanical speed)
8h = Divide by 8 (16-pole motor mechanical speed)
9h = Divide by 9 (18-pole motor mechanical speed)
Ah = Divide by 10 (20-pole motor mechanical speed)
Bh = Divide by 11 (22-pole motor mechanical speed)
Ch = Divide by 12 (24-pole motor mechanical speed)
Dh = Divide by 13 (26-pole motor mechanical speed)
Eh = Divide by 14 (28-pole motor mechanical speed)
Fh = Divide by 15 (30-pole motor mechanical speed)
24 DEAD_TIME_COMP R/W 0h Dead Time Correction applied to calculate power in Power Limit and Closed Loop Power Control modes
0h = Disable
1h = Enable
23-21 FG_BEMF_THR R/W 0h FG output BEMF threshold, phase voltage scaled down based on DYN_VOLT_SCALING_EN
0h = +/- 1mV
1h = +/- 2mV
2h = +/- 5mV
3h = +/- 10mV
4h = +/- 20mV
5h = +/- 30mV
6h = N/A
7h = N/A
20-18 MTR_STOP R/W 0h Motor stop method
0h = Hi-z
1h = Recirculation
2h = Low-side braking
3h = High-side braking
4h = Active spin down
5h = N/A
6h = N/A
7h = N/A
17-14 MTR_STOP_BRK_TIME R/W 0h Brake time during motor stop when configured as Brake Mode
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 15 ms
5h = 25 ms
6h = 50 ms
7h = 75 ms
8h = 100 ms
9h = 250 ms
Ah = 500 ms
Bh = 1000 ms
Ch = 2500 ms
Dh = 5000 ms
Eh = 10000 ms
Fh = 15000 ms
13-11 ACT_SPIN_BRK_THR R/W 0h Duty cycle threshold for motor stop using active spin down, low- and high-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
10-8 BRAKE_DUTY_THRESHOLD R/W 0h Duty cycle threshold for BRAKE pin based low-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
7 AVS_EN R/W 0h AVS enable
0h = Disable
1h = Enable
6-2 CBC_ILIMIT R/W 0h Motor Run CBC current limit threshold. Motor Run current limit threshold (A) = (CBC_ILIMIT - Offset) / (CSA_GAIN * RSENSE). Offset = 0.075V for VREF_SEL = UNI DIRECTIONAL CSA (Values rolls over after 1Bh). Offset = 0V for VREF_SEL = BI-DIRECTIONAL CSA (Values rolls over after 0Fh).
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
11h = 1.7 V
12h = 1.8 V
13h = 1.9 V
14h = 2.0 V
15h = 2.1 V
16h = 2.2 V
17h = 2.3 V
18h = 2.4 V
19h = 2.5 V
1Ah = 2.6 V
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
1 OL_ILIMIT_CONFIG R/W 0h Open loop current limit configuration
0h = Open loop current limit defined by OL_ILIMIT
1h = Open loop current limit defined by CBC_ILIMIT
0 INTEG_ZC_METHOD R/W 0h Commutation method select
0h = ZC based
1h = Integration based

7.7.1.6 CLOSED_LOOP3 Register (Offset = 8Ah) [Reset = 000000A0h]

CLOSED_LOOP3 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP3_TABLE_TABLE.

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Register to configure close loop settings3

Table 7-17 CLOSED_LOOP3 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-29 INTEG_CYCL_THR_LOW R/W 0h Number of BEMF samples per 30° below which commutation method switches from integration to ZC
0h = 3
1h = 4
2h = 6
3h = 8
28-27 INTEG_CYCL_THR_HIGH R/W 0h Number of BEMF samples per 30° above which commutation method switches from ZC to integration
0h = 4
1h = 6
2h = 8
3h = 10
26-25 INTEG_DUTY_THR_LOW R/W 0h Duty cycle below which commutation method switches from integration to ZC
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
24-23 INTEG_DUTY_THR_HIGH R/W 0h Duty cycle above which commutation method switches from ZC to integration
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
22-17 BEMF_THRESHOLD2 R/W 0h BEMF threshold for integration based commutation during falling floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
16-11 BEMF_THRESHOLD1 R/W 0h BEMF threshold for integration based commutation during rising floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
10-8 DYN_DGS_FILT_COUNT R/W 0h Number of samples needed for dynamic degauss check
0h = 3
1h = 6
2h = 9
3h = 12
4h = 15
5h = 20
6h = 30
7h = 40
7-6 DYN_DGS_UPPER_LIM R/W 2h Dynamic degauss voltage upper bound
0h = (VM - 0.09) V
1h = (VM - 0.12) V
2h = (VM - 0.15) V
3h = (VM - 0.18) V
5-4 DYN_DGS_LOWER_LIM R/W 2h Dynamic degauss voltage lower bound
0h = 0.03 V
1h = 0.06 V
2h = 0.09 V
3h = 0.12 V
3-1 DEGAUSS_MAX_WIN R/W 0h Maximum degauss window
0h = 22.5°
1h = 10°
2h = 15°
3h = 18°
4h = 30°
5h = 37.5°
6h = 45°
7h = 60°
0 DYN_DEGAUSS_EN R/W 0h Dynamic degauss detection
0h = Disable
1h = Enable

7.7.1.7 CLOSED_LOOP4 Register (Offset = 8Ch) [Reset = 00000000h]

CLOSED_LOOP4 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CLOSED_LOOP4_TABLE_TABLE.

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Register to configure close loop settings4

Table 7-18 CLOSED_LOOP4 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30 DYN_VOLT_SCALING_EN R/W 0h Dynamic Voltage Scaling Enable
0h = Disable
1h = Enable
29 HIGH_RES_SAMP R/W 0h Bandwidth of control loop.
0h = High bandwidth for control loop.
1h = Low bandwidth for control loop.
28 AVS_LIMIT_HYST R/W 0h AVS current hysteresis. (AVS positive current limit (A) = ((AVS_LIMIT_HYST + AVS_NEG_CURR_LIMIT) * 3 /4095) / (CSA_GAIN * RSENSE))
0h = 20
1h = 10
27-25 AVS_NEG_CURR_LIMIT R/W 0h AVS negative current limit. (AVS negative current limit (A) = (AVS_NEG_CURRENT_LIMIT * 3 /4095) / (CSA_GAIN * RSENSE))
0h = 0
1h = -60
2h = -40
3h = -30
4h = -20
5h = -10
6h = 15
7h = 30
24 RESERVED R/W 0h Reserved
23-22 RESERVED R/W 0h Reserved
21-20 FAST_DEC_DEG_TIME R/W 0h Fast Decel Deglitch Time
0h = 2uS
1h = 4uS
2h = 8uS
3h = 14uS
19 WCOMP_BLANK_EN R/W 0h Enable WCOMP blanking during fast deceleration
0h = Disable
1h = Enable
18-16 FAST_DEC_DUTY_WIN R/W 0h Fast deceleration duty window
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
15-13 FAST_DEC_DUTY_THR R/W 0h Fast deceleration duty threshold
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
12-9 DYN_BRK_CURR_LOW_LIM R/W 0h Fast deceleration dynamic current limit lower threshold. Deceleration current lower threshold (A) = DYN_BRK_CURR_LOW_LIM / (CSA_GAIN * RSENSE). This setting is applicable for VREF_SEL = BI-DIRECTIONAL CSA only.
0h = N/A
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
8 DYNAMIC_BRK_CURR R/W 0h Enable dynamic decrease in current limit during fast deceleration
0h = Disable
1h = Enable
7 FAST_DECEL_EN R/W 0h Fast deceleration enable
0h = Disable
1h = Enable
6-3 FAST_DECEL_CURR_LIM R/W 0h Deceleration current threshold. Fast Deceleration current limit upper threshold (A) = FAST_DECEL_CURR_LIM / (CSA_GAIN * RSENSE). This setting is applicable for VREF_SEL = BI-DIRECTIONAL CSA only.
0h = N/A
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
2-0 FAST_BRK_DELTA R/W 0h Fast deceleration exit speed delta
0h = 0.5 %
1h = 1 %
2h = 1.5 %
3h = 2 %
4h = 2.5 %
5h = 3 %
6h = 4 %
7h = 5 %

7.7.1.8 CONST_SPEED Register (Offset = 8Eh) [Reset = 00000000h]

CONST_SPEED is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_SPEED_TABLE_TABLE.

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Register to configure Constant speed mode settings

Table 7-19 CONST_SPEED Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30 RESERVED R/W 0h Reserved
29-20 SPD_POWER_KP R/W 0h Speed/ Power loop Kp (Kp = SPD_LOOP_KP / 10000)
19-8 SPD_POWER_KI R/W 0h Speed/ Power loop Ki (Ki = SPD_LOOP_KI / 1000000)
7-5 SPD_POWER_V_MAX R/W 0h Upper saturation limit for speed/ power loop
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
4-2 SPD_POWER_V_MIN R/W 0h Lower saturation limit for speed/power loop
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
1-0 CLOSED_LOOP_MODE R/W 0h Closed loop mode
0h = Disabled
1h = Speed Loop
2h = Power Loop
3h = Reserved

7.7.1.9 CONST_PWR Register (Offset = 90h) [Reset = 00000000h]

CONST_PWR is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_CONST_PWR_TABLE_TABLE.

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Register to configure Constant power mode settings

Table 7-20 CONST_PWR Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-15 MAX_SPEED R/W 0h Maximum Speed. (Maximum Speed (Hz) = MAX_SPEED / 16)
14-4 MAX_POWER R/W 0h Maximum power. Maximum power (W) = MAX_POWER*10 mOhm / RSENSE : {For MAX_POWER between 0 to 1023}. Maximum power (W) = (2*MAX_POWER - 1024)*10 mOhm / RSENSE : {For MAX_POWER between 1024 to 2047}.
3-2 CONST_POWER_LIMIT_HYST R/W 0h Hysteresis for input power regulation (% of MAX_POWER). Power Loop regulates power to reference only if the new reference is more than CONST_POWER_LIMIT_HYST
0h = 5 %
1h = 7.5 %
2h = 10 %
3h = 12.5 %
1-0 CONST_POWER_MODE R/W 0h Input power regulation mode
0h = Voltage Control mode
1h = Closed Loop Power Control
2h = Power Limit Control
3h = Reserved

7.7.1.10 150_DEG_TWO_PH_PROFILE Register (Offset = 96h) [Reset = 00000000h]

150_DEG_TWO_PH_PROFILE is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_TWO_PH_PROFILE_TABLE_TABLE.

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Register to configure 150 degree modulation TWO phase duty

Table 7-21 150_DEG_TWO_PH_PROFILE Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-28 TWOPH_STEP0 R/W 0h 150° modulation , Two ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25 TWOPH_STEP1 R/W 0h 150° modulation , Two ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22 TWOPH_STEP2 R/W 0h 150° modulation, Two ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
21-19 TWOPH_STEP3 R/W 0h 150° modulation, Two ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16 TWOPH_STEP4 R/W 0h 150° modulation, Two ph - step duty - 4
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
15-13 TWOPH_STEP5 R/W 0h 150° modulation, Two ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
12-10 TWOPH_STEP6 R/W 0h 150° modulation, Two ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
9-7 TWOPH_STEP7 R/W 0h 150° modulation, Two ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-0 RESERVED R/W 0h reserved bits for algo parameter update

7.7.1.11 150_DEG_THREE_PH_PROFILE Register (Offset = 98h) [Reset = 00000000h]

150_DEG_THREE_PH_PROFILE is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_150_DEG_THREE_PH_PROFILE_TABLE_TABLE.

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Register to configure 150 degree modulation Three phase duty

Table 7-22 150_DEG_THREE_PH_PROFILE Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-28 THREEPH_STEP0 R/W 0h 150° modulation, Three ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25 THREEPH_STEP1 R/W 0h 150° modulation, Three ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22 THREEPH_STEP2 R/W 0h 150° modulation, Three ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
21-19 THREEPH_STEP3 R/W 0h 150° modulation, Three ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16 THREEPH_STEP4 R/W 0h 150° modulation, Three ph - step duty - 4
0h = 0.0 %
1h = 0.5 %
2h = 0.75 %
3h = 0.8375 %
4h = 0.875 %
5h = 0.9375 %
6h = 0.975 %
7h = 0.99 %
15-13 THREEPH_STEP5 R/W 0h 150° modulation, Three ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
12-10 THREEPH_STEP6 R/W 0h 150° modulation, Three ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
9-7 THREEPH_STEP7 R/W 0h 150° modulation, Three ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-5 LEAD_ANGLE_150DEG_ADV R/W 0h Angle advance for 150° modulation
0h = 0°
1h = 5°
2h = 10°
3h = 15°
4-0 RESERVED R/W 0h Reserved

7.7.1.12 REF_PROFILES1 Register (Offset = 9Ah) [Reset = X]

REF_PROFILES1 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_REF_PROFILES1_TABLE_TABLE.

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Register to configure speed profile1

Table 7-23 REF_PROFILES1 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-29 REF_PROFILE_CONFIG R/W 0h Reference Profile Configuration
0h = Duty Control Mode
1h = Linear Mode
2h = Staircase Mode
3h = Forward Reverse Mode
28-21 DUTY_ON1 R/W X Duty_ON1 Configuration. Turn On Duty Cycle (%) = {(DUTY_ON1/255)*100}.
20-13 DUTY_OFF1 R/W X Duty_OFF1 Configuration. Turn Off Duty Cycle (%) = {(DUTY_OFF1/255)*100}.
12-5 DUTY_CLAMP1 R/W X Duty_CLAMP1 Configuration. Duty Cycle for clamping speed (%) = {(DUTY_CLAMP1/255)*100}.
4-0 DUTY_A R/W X 5 MSB bits for Duty Cycle A. Duty Cycle A (%) = {(DUTY_A/255)*100}.

7.7.1.13 REF_PROFILES2 Register (Offset = 9Ch) [Reset = X]

REF_PROFILES2 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_REF_PROFILES2_TABLE_TABLE.

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Register to configure speed profile2

Table 7-24 REF_PROFILES2 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-28 DUTY_A R/W X 3 LSB bits for Duty Cycle A. Duty Cycle A (%) = {(DUTY_A/255)*100}.
27-20 DUTY_B R/W X Duty_B Configuration. Duty Cycle B (%) = {(DUTY_B/255)*100}.
19-12 DUTY_C R/W X Duty_C Configuration. Duty Cycle C (%) = {(DUTY_C/255)*100}.
11-4 DUTY_D R/W X Duty_D Configuration. Duty Cycle D (%) = {(DUTY_D/255)*100}.
3-0 DUTY_E R/W 0h 4 MSB bits for Duty Cycle E. Duty Cycle E (%) = {(DUTY_E/255)*100}.

7.7.1.14 REF_PROFILES3 Register (Offset = 9Eh) [Reset = X]

REF_PROFILES3 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_REF_PROFILES3_TABLE_TABLE.

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Register to configure speed profile3

Table 7-25 REF_PROFILES3 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-27 DUTY_E R/W X 4 LSB bits for Duty Cycle E. Duty Cycle E (%) = {(DUTY_E/255)*100}.
26-19 DUTY_ON2 R/W X Duty_ON2 Configuration. Turn On Duty Cycle (%) = {(DUTY_ON2/255)*100}.
18-11 DUTY_OFF2 R/W X Duty_OFF2 Configuration. Turn Off Duty Cycle (%) = {(DUTY_OFF2/255)*100}.
10-3 DUTY_CLAMP2 R/W X Duty_CLAMP2 Configuration. Duty Cycle for clamping speed (%) = {(DUTY_CLAMP1/255)*100}.
2-1 STEP_HYST_BAND 0h Hysteresis band used for Step changes
0h = 0%
1h = 2%
2h = 4%
3h = 6%
0 RESERVED R/W 0h Reserved

7.7.1.15 REF_PROFILES4 Register (Offset = A0h) [Reset = X]

REF_PROFILES4 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_REF_PROFILES4_TABLE_TABLE.

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Register to configure speed profile4

Table 7-26 REF_PROFILES4 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-23 REF_OFF1 R/W X Turn off Ref Configuration. Turn off Reference % = {(REF_OFF1/255)*100}.
22-15 REF_CLAMP1 R/W X Ref Clamp 1 Configuration. Clamp REF % = {(REF_CLAMP1/255)*100}.
14-7 REF_A R/W X Ref A configuration. Ref A % = {(REF_A/255)*100}.
6-0 REF_B R/W X 7 MSB of REF_B configuration. REF B% = {(REF_B/255)*100}.

7.7.1.16 REF_PROFILES5 Register (Offset = A2h) [Reset = X]

REF_PROFILES5 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_REF_PROFILES5_TABLE_TABLE.

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Register to configure speed profile5

Table 7-27 REF_PROFILES5 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30 REF_B R/W X 1 LSB of REF_B configuration. REF B% = {(REF_B/255)*100}.
29-22 REF_C R/W X REF C configuration. REF C % = {(REF_A/255)*100}.
21-14 REF_D R/W X REF D configuration. REF D % = {(REF_D/255)*100}.
13-6 REF_E R/W X REF E Configuration. REF E% = {(REF_E/255)*100}.
5-0 RESERVED R/W 0h Reserved

7.7.1.17 REF_PROFILES6 Register (Offset = A4h) [Reset = X]

REF_PROFILES6 is shown in #GUID-20220906-SS0T-XZJX-PLMZ-5WSQ9KBNT3DT/ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_ALGORITHM_CONFIGURATION_REF_PROFILES6_TABLE_TABLE.

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Register to configure speed profile6

Table 7-28 REF_PROFILES6 Register Field Descriptions
Bit Field Type Reset Description
31 PARITY R/W 0h Parity bit
30-23 REF_OFF2 R/W X Turn off REF Configuration. Turn off REF % = {(REF_OFF2/255)*100}.
22-15 REF_CLAMP2 R/W X Clamp REF Configuration. Clamp REF % = {(REF_CLAMP2/255)*100}.
14-0 RESERVED R/W X Reserved